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Additive engineering has been regarded as a valuable approach for enhancing the power conversion efficiencies (PCEs) of organic solar cells (OSCs). However, the effective solid additive molecules, especially electron-deficient building blocks, that enhance the PCEs of OSCs are still limited. Herein, two cyano-functionalized highly electron-deficient building blocks, namely 3,6-dibromopyrazine-2-carbonitrile (CNPz) and 3,6-dibromopyrazine-2,5-dicarbonitrile (DCNPz), which feature simple structures and facile synthesis are employed as solid additives to optimize the performance of OSCs. It is found that CNPz can modulate the intermolecular interactions and improve the molecular packing, which is beneficial for charge generation, transport, and collection. As a result, a 19.67% PCE is achieved in the PTQ10/m-BTP-PhC6 binary devices, ranking amongst the highest values for OSCs. Furthermore, the general applicability of solid additives is demonstrated in other organic photovoltaic systems. These findings offer valuable insights into designing and developing novel electron-deficient solid additives to boost the efficiency of OSCs. © 2024 The Royal Society of Chemistry.

Convolutional neural networks (CNNs) have achieved high performance in synthetic aperture radar (SAR) automatic target recognition (ATR). However, the performance of CNNs depends heavily on a large amount of training data. The insufficiency of labeled training SAR images limits the recognition performance and even invalidates some ATR methods. Furthermore, under few labeled training data, many existing CNNs are even ineffective. To address these challenges, we propose a Semi-supervised SAR ATR Framework with transductive Auxiliary Segmentation (SFAS). The proposed framework focuses on exploiting the transductive generalization on available unlabeled samples with an auxiliary loss serving as a regularizer. Through auxiliary segmentation of unlabeled SAR samples and information residue loss (IRL) in training, the framework can employ the proposed training loop process and gradually exploit the information compilation of recognition and segmentation to construct a helpful inductive bias and achieve high performance. Experiments conducted on the MSTAR dataset have shown the effectiveness of our proposed SFAS for few-shot learning. The recognition performance of 94.18\% can be achieved under 20 training samples in each class with simultaneous accurate segmentation results. Facing variances of EOCs, the recognition ratios are higher than 88.00\% when 10 training samples each class.

This paper reviews the NTIRE 2022 Challenge on Super-Resolution and Quality Enhancement of Compressed Video. In this challenge, we proposed the LDV 2.0 dataset, which includes the LDV dataset (240 videos) and 95 additional videos. This challenge includes three tracks. Track 1 aims at enhancing the videos compressed by HEVC at a fixed QP. Track 2 and Track 3 target both the super-resolution and quality enhancement of HEVC compressed video. They require x2 and x4 super-resolution, respectively. The three tracks totally attract more than 600 registrations. In the test phase, 8 teams, 8 teams and 12 teams submitted the final results to Tracks 1, 2 and 3, respectively. The proposed methods and solutions gauge the state-of-the-art of super-resolution and quality enhancement of compressed video. The proposed LDV 2.0 dataset is available at https://github.com/RenYang-home/LDV_dataset. The homepage of this challenge (including open-sourced codes) is at https://github.com/RenYang-home/NTIRE22_VEnh_SR.

Jianyun Ge,1,* Yulin Huang,2,* Yi Zhang,3 Lin Liu,1 Tianyu Gu,1 Xu Liu,1 Lei Yao,1 Mengmeng Cai,1 Jiafeng Sun,1 Jie Song1 1Department of Anesthesiology, The Second Affiliated Hospital of Nantong University, Nantong, Jiangsu 226001, People’s Republic of China; 2Department of Anesthesiology, Affiliated Drum Tower Hospital of Medical School of Nanjing University, Nanjing, Jiangsu 210000, People’s Republic of China; 3Department of Neurosurgery, The Second Affiliated Hospital of Nantong University, Nantong, Jiangsu 226001, People’s Republic of China*These authors contributed equally to this workCorrespondence: Jie SongDepartment of Anesthesiology, The Second Affiliated Hospital of Nantong University, No. 6 North Haier Lane Road, Nantong 226001, Jiangsu, People’s Republic of ChinaEmail sondjiedoc@163.comObjective: To elucidate the neuroprotective function of metformin in suppressing propofol-induced apoptosis of HT-22 cells.Methods: HT-22 cells were treated with 0, 10 or 100 μmol/L propofol, followed by determination of their proliferative ability. Subsequently, changes in proliferation and apoptosis of propofol-treated HT-22 cells induced with metformin were assessed. Apoptosis-associated genes in HT-22 cells were detected by Western blot. At last, regulatory effects of Cav-1 on propofol and metformin-treated HT-22 cells were examined.Results: Propofol treatment dose-dependently decreased proliferative ability and increased apoptosis ability in HT-22 cells, which were partially blocked by metformin administration. Upregulated Bcl-2 and downregulated Bax were observed in propofol-treated HT-22 cells following metformin administration. In addition, Cav-1 level in HT-22 cells was regulated by metformin treatment. Notably, metformin reversed propofol-induced apoptosis stimulation and proliferation decline in HT-22 cells via downregulating Cav-1.Conclusion: In our study, we found that propofol could induce apoptosis of HT-22 cell

This paper presents a unified, radix-4 implementation of turbo decoder, covering multiple standards such as DVB, WiMAX, 3GPP-LTE and HSPA Evolution. The radix-4, parallel interleaver is the bottleneck while using the same turbo-decoding architecture for multiple standards. This paper covers the issues associated with design of radix-4 parallel interleaver to reach to flexible turbo-decoder architecture. Radix-4, parallel interleaver algorithms and their mapping on to hardware architecture is presented for multi-mode operations. The overheads associated with hardware multiplexing are found to be least significant. Other than flexibility for the turbo decoder implementation, the low silicon cost and low power aspects are also addressed by optimizing the storage scheme for branch metrics and extrinsic information. The proposed unified architecture for radix-4 turbo decoding consumes 0.65 mm(2) area in total in 65 nm CMOS process. With 4 SISO blocks used in parallel and 6 iterations, it can achieve a throughput up to 173.3 Mbps while consuming 570 mW power in total. It provides a good trade-off between silicon cost, power consumption and throughput with silicon efficiency of 0.005 mm(2)/Mbps and energy efficiency of 0.55 nJ/b/iter., Funding Agencies|European Commission||Ericson AB||Infineon Austria AG||IMEC||Lund University||KU-Leuven

Digital front-end and Turbo decoder are the two key components in the digital wireless communication system. This thesis will discuss the implementation issues of both digital front-end and Turbo decoder.The structure of digital front-end for multi-standard radio supporting wireless standards such as IEEE802.11n, WiMAX, 3GPP LTE is investigated in the thesis. A top-to-down design methods. 802.11n digital down-converter is designed from Matlab model to VHDL implementation. Both simulation and FPGA prototyping are carried out.As another significant part of the thesis, a parallel Turbo decoder is designed and implemented for 3GPPLTE. The block size supported ranges from 40 to 6144 and the maximum number of iteration is eight.The Turbo decoder will use eight parallel SISO units to reach a throughput up to 150Mits.

Digital front-end and Turbo decoder are the two key components in the digital wireless communication system. This thesis will discuss the implementation issues of both digital front-end and Turbo decoder.The structure of digital front-end for multi-standard radio supporting wireless standards such as IEEE802.11n, WiMAX, 3GPP LTE is investigated in the thesis. A top-to-down design methods. 802.11n digital down-converter is designed from Matlab model to VHDL implementation. Both simulation and FPGA prototyping are carried out.As another significant part of the thesis, a parallel Turbo decoder is designed and implemented for 3GPPLTE. The block size supported ranges from 40 to 6144 and the maximum number of iteration is eight.The Turbo decoder will use eight parallel SISO units to reach a throughput up to 150Mits.

This paper presents a parameterized parallel Turbo decoder for 3GPP LTE terminals. To support the high peak data-rate defined in the forthcoming 3GPP LTE standard, turbo decoder with a throughout beyond 150 Mbit/s is needed as a key component of the radio baseband chip. By exploiting the tradeoff of precision, speed and area consumption, a turbo decoder with eight parallel SISO units is implemented to meet the throughput requirement. The turbo decoder is synthesized, placed and routed using 65 nm CMOS technology. It achieves a throughput of 152 Mbit/s and occupies an area of 0.7 mm2 with estimated power consumption being 650 mW.