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This study analyzes the effects of the punch-through stop (PTS) layer and well depth in a bulk FinFET SRAM cell on the fraction of charge generated by an ion impact that is collected by the FinFET channel. More than 1700 3D TCAD simulations have been performed to obtain a detailed map of the sensitivity areas in a full cell 6-T SRAM 22 nm bulk-FinFET process. The influence of the well depth on the charge collected by the drain devices of the SRAM cell has been studied, and it has been concluded that the collected charge can be reduced down to 300% simply by modifying the depth of the well, without affecting the performance of the cell. Different PTS layer depths have been analyzed in order to calculate which value minimizes the impact of the charge generated by an ion during its track along the FinFET body. The simulations carried out allow to conclude that the incorporation of a PTS layer not only reduces the leakage current, but also reduces the amount of charge, delivered by the ion, that reaches the drain region. Simulation results also show that the fraction of the charge generated by the ion impact, which is collected by the drain, mainly depends on the depth of the wells, whereas the PTS layer hardly modifies the collected charge., Peer Reviewed, Postprint (published version)

In this paper, we present a new method to mitigate the effect of the charge collected by trigate FinFET devices after an ionizing particle impact. The method is based on the creation of an internal structure that generates an electrical field that drives the charge generated by the ion track out of the sensitive device terminals. This electrical field is generated with the insertion of complementary doped regions near the active region of the device. We analyze the influence of the distance of those regions to the device, their depth into the substrate and their doping concentration to determine the optimal implementation which minimizes the collected charge. The impact on the device performance in terms of leakage current, threshold voltage, maximum transconductance and subthreshold voltage swing has also been investigated. Our results show that the added structures introduce negligible effects in performance degradation and total leakage current, at the cost of a small increase in area. The simulations performed with technology computer-aided design numerical (TCAD) tools in 22nm bulk FinFET technology show that the amount of charge collected by the device terminals can be reduced up to 50% for a linear energy transfer (LET) of 60 MeV-cm2/mg., Peer Reviewed, Postprint (published version)