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6 results on '"France Télécom Recherche '

1. A new contactless smartcard IC using an on-chip antenna and an asynchronous micro-controller

Author

Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), France Télécom Recherche & Développement (FT R&D) ; France Télécom, Abrial, A., Bouvier, J., Renaudin, M., Senn, P., Vivet, P., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), France Télécom Recherche & Développement (FT R&D) ; France Télécom, Abrial, A., Bouvier, J., Renaudin, M., Senn, P., and Vivet, P.

Abstract

A new generation of Contactless Smartcard Chip is described. The Contactless Smartcard Chip integrates an on-chip coil connected to a power reception system and an emitter/receiver module compatible with the ISO 14443 standard, together with an asynchronous Quasi Delay Insensitive (QDI) 8-bit micro-controller. Beyond the contactless smartcard application field, this new chip demonstrates that System-on-Chip integrating power reception and management, radio-frequency communication and signal processing are feasible. The chip associates analog/digital parts as well as synchronous/asynchronous logics and has been fabricated in a CMOS 6 metal layers .25µm technology from STMicroelectronics.

2. Svoboda-Tung division with no compensation

Author

France Télécom Recherche et Développement (FTR&D) ; France Télécom, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Montalvo, L.-A., Guyot, A., France Télécom Recherche et Développement (FTR&D) ; France Télécom, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Montalvo, L.-A., and Guyot, A.

Abstract

ISBN: 0818669055, The development of a new general radix-b division algorithm, based on the Svoboda-Tung division, suitable for VLSI implementation is presented. The new algorithm overcomes the drawbacks of the Svoboda-Tung techniques that have prevented the VLSI implementation. First of all, the proposed algorithm is valid for any radix b>or=2; and next, it avoids the possible compensation due to overflow on the iteration by re-writing the two most significant digits of the remainder. An analysis of the algorithm shows that a known radix-2 and two recently published radix-4 division algorithms are particular cases of this general radix-b algorithm. Finally, since the new algorithm is valid only for a reduced range of the IEEE normalised divisor, a pre-scaling technique, based on the multiplication of both the operands by a stepwise approximation to the reciprocal of the divisor is also presented.

3. Combinational digit-set converters for hybrid radix-4 arithmetic

Author

France Télécom Recherche et Développement (FTR&D) ; France Télécom, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Montalvo, L.-A., Guyot, A., France Télécom Recherche et Développement (FTR&D) ; France Télécom, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Montalvo, L.-A., and Guyot, A.

Abstract

ISBN: 0818665653, Two pure combinational radix-4 digit-set converters for use in hybrid arithmetic are presented. The conventional to minimally redundant balanced signed-digit set converter is very simple and has zero cost and delay in terms of gates. The balanced to conventional digit-set converter performs the conversion "on the fly" with the generation of the balanced signed-digits, from the most significant to the least significant one; it has an O(1) delay (i.e. constant and independent of the length n of the number), an O(n/sup 2/) cost and a regular structure suitable for VLSI implementation. A review of the principles of hybrid addition/subtraction was previously presented (N. Takagi et al., 1985).

4. Watershed parallel algorithm for asynchronous processors array

Author

France Télécom Recherche & Développement (FT R&D) ; France Télécom, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Galilee, B., Mamalet, F., Renaudin, M., Coulon, P.Y., France Télécom Recherche & Développement (FT R&D) ; France Télécom, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Galilee, B., Mamalet, F., Renaudin, M., and Coulon, P.Y.

Abstract

ISBN: 0780373049, A joint algorithm-architecture analysis leads to a new version of picture segmentation system adapted to multimedia mobile terminal constraints. The asynchronous processors network, with a granularity level of one processor per pixel, based on data flow model, takes less than 10 mu s to segment a SQCIF $88*72 pixels - image (about 2000 times faster than the classical sequential watershed algorithms). The main originality of the proposed algorithm is only one global synchronization point is needed in order to complete the segmentation transformation, instead of the three (or more) classical points: minima detection, labelization and flooding. Our system tends to cope with multimedia mobile phones constraints, i.e. real time computing circuit, low power. We have simulated and validated this system thanks to "SystemC" library; VHDL synchronous prototyping shows up results accordingly.

5. The ARESA Project: Facilitating Research, Development and Commercialization of WSNs

Author

France Télécom Recherche & Développement (FT R&D) ; France Télécom, VERIMAG (VERIMAG - IMAG) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Coronis Systems, S.A. ; Coronis Systems, S.A., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Laboratoire Logiciels Systèmes Réseaux (LSR - IMAG) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), ARES (CITI Insa Lyon / INRIA Grenoble Rhône-Alpes) ; INRIA - Institut National des Sciences Appliquées [INSA] - Lyon, ARESA, ANR-05-RNRT-017, ARESA, Système Enfoui et Réseaux de Capteurs(2005), Dohler, Mischa, Barthel, Dominique, Maraninchi, Florence, Mounier, Laurent, Aubert, Stéphane, Dugas, Christophe, Buhrig, A., Paugnat, Franck, Renaudin, Marc, Duda, Andrzej, Heusse, Martin, Valois, Fabrice, France Télécom Recherche & Développement (FT R&D) ; France Télécom, VERIMAG (VERIMAG - IMAG) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Coronis Systems, S.A. ; Coronis Systems, S.A., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Laboratoire Logiciels Systèmes Réseaux (LSR - IMAG) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), ARES (CITI Insa Lyon / INRIA Grenoble Rhône-Alpes) ; INRIA - Institut National des Sciences Appliquées [INSA] - Lyon, ARESA, ANR-05-RNRT-017, ARESA, Système Enfoui et Réseaux de Capteurs(2005), Dohler, Mischa, Barthel, Dominique, Maraninchi, Florence, Mounier, Laurent, Aubert, Stéphane, Dugas, Christophe, Buhrig, A., Paugnat, Franck, Renaudin, Marc, Duda, Andrzej, Heusse, Martin, and Valois, Fabrice

Abstract

International audience, Within academia, wireless sensor networks have witnessed a tremendous upsurge in the last decade, which is mainly attributed to their unprecedented operating conditions and hence unlimited research challenges. Within industry, the projected business opportunities are huge with, e.g. according to Frost & Sullivan, an expected market size of approximately $2b by 2012 at a compound annual growth rate of 41.9%, therefore causing the interest in this technology to augment dramatically. The aim of the ARESA project is to capitalize on this academic and industrial momentum and provide clear and knowledgeable guidelines and solutions related to the research, development and commercialization of this emerging technology. The diverse background of the involved partners facilitates unprecedented insights into the design process from conception to revenue makings. This paper aims at summarizing some key issues one encounters when researching medium access control and routing protocols, formally verifying their proper functioning, developing low-power hardware, and finally commercializing wireless sensor networks.

6. Application of fast layout synthesis environment to dividers evaluation

Author

Laboratoire Méthodologie et Architecture des Systèmes Informatiques (MASI) ; Université Pierre et Marie Curie (UPMC) - Paris VI, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), France Télécom Recherche et Développement (FTR&D) ; France Télécom, Houelle, A., Mehrez, H., Vaucher, Ch., Montalvo, L.-A., Guyot, A., Laboratoire Méthodologie et Architecture des Systèmes Informatiques (MASI) ; Université Pierre et Marie Curie (UPMC) - Paris VI, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), France Télécom Recherche et Développement (FTR&D) ; France Télécom, Houelle, A., Mehrez, H., Vaucher, Ch., Montalvo, L.-A., and Guyot, A.

Abstract

ISBN: 0818670894, Experience has shown that generator programs are quite often written by VLSI designers, as they hold the empirical knowledge better than anyone. However, their ability does not necessarily include programming and debugging skills: these designers have to focus on the problem at hand not on the tools or the language they use to solve it. GenOptim has been created to quickly design efficient IEEE 754 floating-point macro-cell generators that do not rely on particular target technologies. Whereas the design of fast and efficient adders, multipliers and shifters is well understood division and square root remain a serious design challenge. GenOptim was used to quickly evaluate new divider architectures.

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