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The adoption of convolutional neural network algorithms requires an increasing number of multiply-and-accumulate operations. Compute-in-memory leverages the spatial arrangement of static random access memory (SRAM) cells to increase parallelism and reduce power consumption, overcoming repeated data access and movement from the memory to the computing unit in von Neumann architectures.In the proposed work, an SRAM cell with six transistors is described, explaining how the multiply-and-accumulate operation is performed and how its architecture is suitable for compute-in-memory. As multiple SRAM cells are accessed at the same time, the importance of static noise margin is discussed in the read and hold operations and the 8T Single-Ended SRAM cell presented to overcome read-disturbance issues.The SRAM cells are designed in 16 nm FinFET CMOS process and simulated to calculate the hold and read static noise margins in the nominal and PVT corners. Specifically, the 6T SRAM cell exhibits nominal hold and read static noise margin values of 355.8 mV and 188.0 mV respectively. The 8T Single-Ended SRAM cell has equivalent nominal hold and read static noise margin values of 354.6 mV, overcoming read disturbance and being a feasible candidate for reliable compute-in-memory arrays.

Está depositada la versión preprint del artículo, In this paper, the time-dependent dielectric breakdown (TDDB) in sub-1-nm equivalent oxide thickness (EOT) n-type bulk FinFETs is studied. The gate stacks consist of an IMEC clean interfacial layer, atomic layer deposition HfO2 high-kappa and TiN metal electrode. For the 0.8-nm EOT FinFETs, it is found that TDDB lifetime is consistent with results of planar devices for areas around 10(-8) cm(2), implying that the FinFET architecture does not seem to introduce new failure mechanisms. However, for devices with smaller area, the extrapolated voltage at a ten-year lifetime for soft breakdown (SBD) does not meet the specifications, and as a consequence, the SBD path wear-out will have to be included in the final extrapolation. Furthermore, it is shown that for EOTs smaller than 0.8 nm, the TDDB reliability on n-type FinFETs is challenged by the high leakage currents., Ministerio de Ciencia e Innovación (España), Depto. de Estructura de la Materia, Física Térmica y Electrónica, Fac. de Ciencias Físicas, TRUE, pub

For several decades, the development of metal-oxide-semiconductor field-effect transistors have made available to us better circuit time and efficiency per function with each successive generation of CMOS technology. However, basic product and manufacturing technology limitations will make continuing transistor scaling difficult in the sub-32 nm zone. Field impact transistors with fins were developed. offered as a viable solution to the scalability difficulties. Fin field effect transistors can be made in the same way as regular CMOS transistors, allowing for a quick transition to production. The use of inserted-oxide FinFET technology was presented as a solution to continue transistor scaling. Due to gate fringing electric fields through the added oxide (SiO2) layers, the electromagnetic integrity of an iFinFET is superior to that of a FinFET. We discovered that the proposed mobility model functions admirably and that the Joule effect mostly influences the drain current and the heat source. The major goal of this work is to compare the performance characteristics of combinational logic using CMOS and FinFET technology. The inverting gate is modelled in HSPICE simulation on a 32nm transistor size utilising CMOS and FinFET structures, and respective performances, such as energy consumed, are examined.

There is a strong need for a large band gap pFET device with good performance for an efficient high voltage CMOS platform for power conversion applications. GaN is a leading choice of material for high power applications. GaN HEMTs are already commercially used in high power conversion systems. However, the performance of the GaN pFETs have not been attractive enough for a GaN based CMOS power conversion technology.Work in this dissertation focuses on improving the on-current of hole channel GaN transistors while maintaining normally off operation. Lower hole mobility requires a much higher hole channel charge to achieve an on-resistance of the same order as GaN HEMTs. One approach is to distribute the total carriers in multiple parallel channels and modulate these parallel channels independently. A Mg-doped GaN/AlGaN superlattice (SL) is one way to get multiple parallel hole channels. The effects of different superlattice parameters were studied using self-consistent Poisson-Schrodinger solver. Using MOCVD grown GaN/AlGaN superlattice, FinFET devices were designed, fabricated, and characterized. The first generation of devices employing MIS gate structure showed normally-on operation with >100 mA/mm. Next, Schottky gate structures were used to achieve normally-off operation. These devices used a dry etch induced sidewall tunnel junction contacts, which led to turn-on voltage in the device output characteristics. MOCVD regrown p+ GaN contact layer process was developed to remove this turn-on voltage. Both blanket and selective area regrown contact process were optimized. Finally, the regrown contact process was integrated with the FinFET process. MOCVD regrown contacts around the fins led to FinFET devices with normally-off operation, >60 mA/mm on-current and 42 V breakdown voltage.

The Fin Field-Effect Transistor (FinFET) technology became the most promising approach to enable the downscaling of technological nodes below the 20 nm threshold. However, the introduction of new technology nodes for embedded memories such as SRAMs, especially for even smaller nodes such as 10 and 5 nm, gives rise to new manufacturing failure mechanisms; these could both impact the yield and the outgoing product quality in the absence of appropriate diagnosis and test solutions. Therefore, there is a need for effective yet cost-efficient test and diagnosis solutions. This thesis contributes to fault modeling, test development, and diagnosis of FinFET based SRAM., Quantum & Computer Engineering

We present a novel Pelgrom-based predictive (PBP) model to estimate the impact of variability on the on-current of different state-of-the-art semiconductor devices. In this work, we focus on two of the most problematic sources of variability, the metal grain granularity (MGG) and the line edge roughness (LER). This model allows us to make an accurate prediction of the on-current standard deviation , being the relative error of the predicted data lower than 8% in 92% of the studied cases. The PBP model entails an immense reduction in the computational cost since once it is calibrated for an architecture, the prediction of the impact of a variability on devices with any given dimension can be made without any further simulations. This model could be useful for predicting the effect of variability on future technology nodes

SRAM Physical Unclonable Functions (PUFs) are among other things today commercially used for secure primitives such as key generation and authentication. The quality of the PUFs and hence the security primitives, depends on intrinsic variations which are technology dependent. Therefore, to sustain the commercial usage of PUFs for cutting-edge technologies, it is important to properly model and evaluate their reliability. In this work, we evaluate the SRAM PUF reliability using within class Hamming distance (WCHD) for 16nm, 14nm, and 7nm using simulations and silicon validation for both low-power and high-performance designs. The results show that our simulation models and expectations match with the silicon measurements. From the experiments, we conclude the following: (1) SRAM PUF is reliable in advanced FinFET technology nodes, i.e., the noise is low in 16nm, 14nm, and 7nm, (2) temperature variations have a marginal impact on the reliability, and (3) both low-power and high-performance SRAMs can be used as a PUF without excessive need of error correcting codes (ECCs)., Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public., Computer Engineering, Quantum & Computer Engineering

This study analyzes the effects of the punch-through stop (PTS) layer and well depth in a bulk FinFET SRAM cell on the fraction of charge generated by an ion impact that is collected by the FinFET channel. More than 1700 3D TCAD simulations have been performed to obtain a detailed map of the sensitivity areas in a full cell 6-T SRAM 22 nm bulk-FinFET process. The influence of the well depth on the charge collected by the drain devices of the SRAM cell has been studied, and it has been concluded that the collected charge can be reduced down to 300% simply by modifying the depth of the well, without affecting the performance of the cell. Different PTS layer depths have been analyzed in order to calculate which value minimizes the impact of the charge generated by an ion during its track along the FinFET body. The simulations carried out allow to conclude that the incorporation of a PTS layer not only reduces the leakage current, but also reduces the amount of charge, delivered by the ion, that reaches the drain region. Simulation results also show that the fraction of the charge generated by the ion impact, which is collected by the drain, mainly depends on the depth of the wells, whereas the PTS layer hardly modifies the collected charge., Peer Reviewed, Postprint (published version)

Silicon height, width, and number of 3D stacked nanosheet layers are optimized in this paper to achieve lower power consumption, enhanced integration density, and higher performance with gate all-around (GAA) 3D stacked nanosheet transistors. Electrical characteristics of vertically stacked nanosheet transistors are compared with FinFETs under equal silicon area and ON current constraints. Assuming a tight vertical silicon sheet pitch of 5nm, test circuits with the vertically stacked nanowires provide comparable speed with active mode energy consumption, silicon area, and idle mode leakage power consumption savings of up to 40.24%, 21.81%, and 63.58%, respectively, as compared to FinFETs in a 5nm CMOS technology. © 2022 IEEE.

This article investigates the fin- and finger-number dependence of the total ionizing dose (TID) degradation in 16-nm bulk Si FinFETs at ultrahigh doses. n- and p-FinFETs designed with different numbers of fins and fingers are irradiated up to 500 Mrad(SiO2) and then annealed for 24 h at 100 °C. The TID responses of nFinFETs are insensitive to the fin number, as dominated by border and interface trap generation in shallow trench isolation (STI) and/or gate oxide. However, pFinFETs show a visible fin-number dependence with worst tolerance of transistors with the smallest number of fins. The fin number dependence may be related to a larger charge trapping in STI located at the opposite lateral sides of the first and last fins. In addition, both n- and p-FinFETs exhibit an almost TID insensitivity to the finger number. During the design of integrated circuits, the TID tolerance of electronic systems can be enhanced by preferably using transistors with a higher number of fins than fingers.

This article investigates the device variability induced by the total ionizing dose (TID) effects in a commercial 16-nm bulk nFinFETs, using specially designed test structures and measurement procedures aimed at maximizing the matching between devices. DC static characteristic measurements show that below 100 Mrad(SiO2) the device variability is slightly affected by the total accumulated dose. However, when the total dose reaches 100 Mrad(SiO2), the device variability increases significantly showing a correlation with pre-irradiation electrical responses of the devices. Transistors characterized by higher drain current exhibit the worst TID degradation. This phenomenon is likely due to the impact of random dopant fluctuations on the TID effects and/or to variations in the hydrogen concentration responsible for the TID-induced interface traps.

open, In the last 30 years, Mobile Telecommunication (TLC) electronics proved to be one of the major driving motors in the development of new Complementary Metal-OxideSemiconductor (CMOS) technologies. This limited branch of the electronics world managed to move billions of dollars worldwide, some of which unavoidably ended up in financing advanced research projects to answer market demands. People all around the world ask for extremely performing portable devices, faster, more reliable, low power consuming and with impressive memory capability. To answer all these requests, physics and engineers developed new and incredibly down-scaled technology nodes, which met the high speed and low power consumption requirement, granting an impressive circuital density. Nowadays foundries such as TSMC or Samsung are able to manufacture incredibly small transistor devices, with channel length in the order of only 7 nm and transition frequency in the order of several hundreds of GHz. This situation has become extremely favorable for the development of high-performance digital devices, which are able to reach speed and memory capability previously unbelievable. Nonetheless, also analog building blocks must be integrated in deeply down-scaled node, in order to adapt with digital ICs. First task of this thesis work is to develop analog ICs in deep sub-micron technology nodes, such as 28 nm bulk-CMOS and 16 nm FinFET (Fin Field Effect Transistor). This has been accomplished facing several difficulties given by the very poor analog behavior of such advanced technologies, especially in terms of low transistor intrinsic gain and limited signal headroom, caused by the low supply voltage. The second task of this work is to develop these same analog ICs in order that they meet requirements of the most advanced TLC standards, such as LTE and 5G. The increased number of portable devices worldwide made in fact unavoidable the introduction of new communication standards, in order to face the huge nu, Negli ultimi 30 anni, l’elettronica per le Telecomunicazioni Wireless si è dimostrata una delle forze trainanti nello sviluppo delle nuove tecnologie Complementary Metal-OxideSemiconductor (CMOS). Questa piccola branca del vasto mondo dell’elettronica è infatti in grado di smuovere, in tutto il mondo, miliardi di dollari, molti dei quali inevitabilmente finiscono per finanziare gli avanzati progetti di ricerca in grado di rispondere alle domande del Mercato. In tutto il mondo, le persone chiedono nuovi dispositivi portatili, più performanti, più veloci, più affidabili, che consumino poca potenza e che abbiano una maggiore capacità di immagazzinare dati. Per rispondere a queste richieste, fisici e ingegneri hanno sviluppato nuovi e incredibili nodi tecnologici ultra-scalati, che soddisfano i requisiti di velocità e bassi consumi, garantendo un’impressionante densità circuitale. Al giorno d’oggi, le fonderie come TSMC e Samsung sono in grado di realizzare transistor estremamente piccoli, con lunghezze di canale di soli 7 nm e frequenze di transizione nell’ordine delle centinaia di GHz. Questo sviluppo si rivela estremamente favorevole per lo sviluppo di dispositivi digitali ad alte prestazioni, che raggiungono performance di velocità e di memoria prima inimmaginabili. Non di meno, anche i blocchi analogici devono essere integrati in questi nodi estremamente scalati, in modo da potersi adattare ai circuiti integrati (IC) digitali. Primo obiettivo di questo lavoro di tesi è, quindi, lo sviluppo di IC analogici in nodi tecnologici deep-submicron, come il 28 nm bulk-CMOS e il 16 nm FinFET (Fin Field Effect Transistor). Questo obiettivo è stato raggiunto affrontando diverse difficoltà date dalle scarse performance analogiche di queste tecnologie avanzate, tra cui un basso guadagno intrinseco e una limitata tensione di alimentazione. Il secondo obiettivo di questo lavoro è stato sviluppare questi stessi IC in modo che fossero compatibili con i più moderni standard per telec, 0, open, Fary, F

Manufacturing defects in FinFET SRAMs can cause hard-to-detect faults such as Undefined State Faults (USFs). Detection of USFs is not trivial, as they may not lead to incorrect functionality. Nevertheless, undetected USFs may have a severe impact on the memory's quality: they can cause random read outputs, which might lead to test escapes and no-trouble-found devices later when the device is already in the field, as well as compromise the circuit's quality by reducing the memory cell's Static Noise Margin (SNM). Therefore, the detection of USF is critical. This paper proposes a test solution to improve the detection of USFs in FinFET SRAMs. To achieve this, we first analyze the impact of USFs on the cell's SNM and bitline swing during read operations. Then, we perform an experimental study of stress conditions' (SCs) impact on sensitizing and detecting USFs. Finally, we propose a dedicated Design-For-Testability (DFT) scheme for FinFET SRAMs to detect such faults. This scheme introduces a small area overhead while significantly improving USF detection. Hence, using the proposed DFT leads to fewer test escapes and higher-quality FinFET SRAMs., Computer Engineering, Quantum & Computer Engineering

Manufacturing defects in FinFET SRAMs can cause hard-to-detect faults such as Random Read Faults (RRFs). Detection of RRFs is not trivial, as they may not lead to incorrect outputs. Undetected RRFs become test escapes, which might lead to no-trouble-found devices and early in-field failures. Therefore, the detection of RRFs is of utmost importance. This paper proposes test solutions to detect RRFs and reduce test escapes. To achieve this, we first statistically analyze the failure rate due to RRFs, followed by an experimental study of stress conditions’ (SCs) impact on detecting RRFs, such as test algorithms, supply voltage, and temperature. Based on the results, we propose a new Design-For-Testability (DFT) scheme for FinFET SRAMs to detect such faults using SCs that improve the detection rate of RRFs. This scheme introduces a negligible area and test time overhead while significantly enhancing RRF detection. Hence, using the proposed DFT leads to reduced test escapes and, consequently, higher-quality FinFET SRAMs., Computer Engineering, Quantum & Computer Engineering

Quantum computers have gained widespread interest as they can potentially solve problems that are intractable even for today’s supercomputers, such as the simulation of quantum systems as initially proposed by Feynman. To achieve such tremendous progress, a quantum computer relies on processing the information stored in quantum bits (qubits), the fundamental units of quantum computation, similar to the bits in a classical (i.e., non-quantum) processor. In general, a quantum processor comprising several qubits is connected through a quantum-to-classical interface consisting of classical electrical circuits for manipulating and reading out their quantum state. The accuracy of an operation on a qubit is characterized using the fidelity, which is 100 % in case of a perfect operation. In practice, a fidelity between 99 % and 99.9 % is typically achieved in today’s experiments with less than 100 qubits, limited by non-idealities in the control signals and by the implementation of the physical qubit itself. Since such qubit fidelities are too low to execute relevant quantum algorithms, quantum error correction schemes have been developed which rely on a much larger number of qubits to correct for possible errors, resulting in the need for quantum processors with thousands or millions of qubits. Solid-state qubits promise the largescale integration required to scale to millions of qubits, as they exploit the lithographic fabrication techniques borrowed from the semiconductor industry. However, state-of-theart solid-state qubits, such as transmons and single-electron spin qubits, must be typically cooled to cryogenic temperatures in a dilution refrigerator to exhibit quantum behavior. Because of the limited number of qubits (< 100) in state-of-theart solid-state quantum processors, the classical controller is currently implemented by general-purpose instruments or by tailor-made controllers operating at room temperature connected via several wires to the qubits in the cry, Quantum Circuit Architectures and Technology

In this article, we introduce a fractional-N all-digital phase-locked loop (ADPLL) architecture based on a single LC-tank, featuring an ultra-wide tuning range (TR) and optimized for ultra-low area in 10-nm FinFET CMOS. Underpinned by excellent switches in the FinFET technology, a high turn-on/off capacitance ratio of LC-tank switched capacitors, in addition to an adjustable magnetic coupling technique, yields almost an octave TR from 10.8 to 19.3GHz. A new method to compensate for the tracking-bank resolution can maintain its quantization noise level over this wide TR. A new scheme is adopted to overcome the metastability resolution problem in a fractional-N ADPLL operation. A low-complexity TDC gain estimator reduces the digital core area by progressive averaging and time-division multiplexing. Among the published fractional-N PLLs with an area smaller than 0.1mm2, this work achieves an rms jitter of 725fs in an internal fractional-N mode of ADPLL's phase detector (2.7-4.825GHz) yielding the best overall jitter figure-of-merit (FOM) of -232dB. This topology features small area (0.034mm2), wide TR (56.5%) and good supply noise rejection (1.8%/V), resulting in FOMs with normalized TR (FOMT) of -247dB, and normalized TR and area (FOMTA) of -262dB., Accepted Author Manuscript, Electronics

This article investigates the total ionizing dose (TID) degradation mechanisms of 16-nm bulk Si FinFETs at ultrahigh doses. n- and p-FinFETs with several channel lengths are irradiated up to 1 Grad(SiO2) and then annealed for 24 h at 100 °C. Irradiated devices show significant degradation in transconductance and OFF-state leakage currents with slight subthreshold stretch-out and negligible threshold voltage shifts. At doses up to 10 Mrad(SiO2), the TID response is dominated by positive trapped charges in the shallow trench isolation (STI). At ultrahigh doses approaching 1 Grad(SiO2), dc static measurements suggest generation of trapped charge at the STI/Si interface and/or at the corner between the STI and the gate dielectric. The TID sensitivity depends on the bias condition and channel length. Halo implantations fortuitously increase the radiation tolerance of short-channel FinFETs due to the increased channel doping caused by the overlap of the source and the drain halos. The worst degradation is found when a high electric field is applied to the gate during irradiation.

Negli ultimi 30 anni, l’elettronica per le Telecomunicazioni Wireless si è dimostrata una delle forze trainanti nello sviluppo delle nuove tecnologie Complementary Metal-OxideSemiconductor (CMOS). Questa piccola branca del vasto mondo dell’elettronica è infatti in grado di smuovere, in tutto il mondo, miliardi di dollari, molti dei quali inevitabilmente finiscono per finanziare gli avanzati progetti di ricerca in grado di rispondere alle domande del Mercato. In tutto il mondo, le persone chiedono nuovi dispositivi portatili, più performanti, più veloci, più affidabili, che consumino poca potenza e che abbiano una maggiore capacità di immagazzinare dati. Per rispondere a queste richieste, fisici e ingegneri hanno sviluppato nuovi e incredibili nodi tecnologici ultra-scalati, che soddisfano i requisiti di velocità e bassi consumi, garantendo un’impressionante densità circuitale. Al giorno d’oggi, le fonderie come TSMC e Samsung sono in grado di realizzare transistor estremamente piccoli, con lunghezze di canale di soli 7 nm e frequenze di transizione nell’ordine delle centinaia di GHz. Questo sviluppo si rivela estremamente favorevole per lo sviluppo di dispositivi digitali ad alte prestazioni, che raggiungono performance di velocità e di memoria prima inimmaginabili. Non di meno, anche i blocchi analogici devono essere integrati in questi nodi estremamente scalati, in modo da potersi adattare ai circuiti integrati (IC) digitali. Primo obiettivo di questo lavoro di tesi è, quindi, lo sviluppo di IC analogici in nodi tecnologici deep-submicron, come il 28 nm bulk-CMOS e il 16 nm FinFET (Fin Field Effect Transistor). Questo obiettivo è stato raggiunto affrontando diverse difficoltà date dalle scarse performance analogiche di queste tecnologie avanzate, tra cui un basso guadagno intrinseco e una limitata tensione di alimentazione. Il secondo obiettivo di questo lavoro è stato sviluppare questi stessi IC in modo che fossero compatibili con i più moderni stan, In the last 30 years, Mobile Telecommunication (TLC) electronics proved to be one of the major driving motors in the development of new Complementary Metal-OxideSemiconductor (CMOS) technologies. This limited branch of the electronics world managed to move billions of dollars worldwide, some of which unavoidably ended up in financing advanced research projects to answer market demands. People all around the world ask for extremely performing portable devices, faster, more reliable, low power consuming and with impressive memory capability. To answer all these requests, physics and engineers developed new and incredibly down-scaled technology nodes, which met the high speed and low power consumption requirement, granting an impressive circuital density. Nowadays foundries such as TSMC or Samsung are able to manufacture incredibly small transistor devices, with channel length in the order of only 7 nm and transition frequency in the order of several hundreds of GHz. This situation has become extremely favorable for the development of high-performance digital devices, which are able to reach speed and memory capability previously unbelievable. Nonetheless, also analog building blocks must be integrated in deeply down-scaled node, in order to adapt with digital ICs. First task of this thesis work is to develop analog ICs in deep sub-micron technology nodes, such as 28 nm bulk-CMOS and 16 nm FinFET (Fin Field Effect Transistor). This has been accomplished facing several difficulties given by the very poor analog behavior of such advanced technologies, especially in terms of low transistor intrinsic gain and limited signal headroom, caused by the low supply voltage. The second task of this work is to develop these same analog ICs in order that they meet requirements of the most advanced TLC standards, such as LTE and 5G. The increased number of portable devices worldwide made in fact unavoidable the introduction of new communication standards, in order to face the huge nu

Fin Field-Effect Transistor (FinFET) technology enables the continuous downscaling of Integrated Circuits (ICs), using the Complementary Metal-Oxide Semiconductor (CMOS) technology in accordance with the More Moore domain. Despite demonstrating improvements on short channel effect and overcoming the growing leakage problem of planar CMOS technology, the continuity of feature size miniaturization tends to increase sensitivity to Single Event Upsets (SEUs) caused by ionizing particles, especially in blocks with higher transistor densities such as Static Random-Access Memories (SRAMs). Variation during the manufacturing process has introduced different types of defects that directly affect the SRAM's reliability, such as weak resistive defects. As some of these defects may cause dynamic faults, which require more than one consecutive operation to sensitize the fault at the logic level, traditional test approaches may fail to detect them, and test escapes may occur. These undetected faults, associated with weak resistive defects, may affect the FinFET-based SRAM reliability during its lifetime. In this context, this paper proposes to investigate the impact of ionizing particles on the reliability of FinFET-based SRAMs in the presence of weak resistive defects. Firstly, a TCAD model of a FinFET-based SRAM cell is proposed allowing the evaluation of the ionizing particle’s impact. Then, SPICE simulations are performed considering the current pulse parameters obtained with TCAD. In this step, weak resistive defects are injected into the FinFET-based SRAM cell. Results show that weak defects can positively or negatively influence the cell reliability against SEUs caused by ionizing particles., Computer Engineering, Quantum & Computer Engineering

This paper presents a new energy efficient N-bit barrel shifter using IG FinFET in 20 nm technology. The independent gate based FinFET device having more attractive features than standard CMOS technology. The proposed N-bit barrel shifter using independent gate FINFET device reduces the low power consumption over MOSFET and simulation results are performed using H spice software. In this work, it is presented the electrical analysis in terms of signal delay propagation and energy consumption of compacted barrel circuit for shifting operation.

Building a large-scale quantum computer requires the co-optimization of both the quantum bits (qubits) and their control electronics. By operating the CMOS control circuits at cryogenic temperatures (cryo-CMOS), and hence in close proximity to the cryogenic solid-state qubits, a compact quantum-computing system can be achieved, thus promising scalability to the large number of qubits required in a practical application. This work presents a cryo-CMOS microwave signal generator for frequency-multiplexed control of 4\times 32 qubits (32 qubits per RF output). A digitally intensive architecture offering full programmability of phase, amplitude, and frequency of the output microwave pulses and a wideband RF front end operating from 2 to 20 GHz allow targeting both spin qubits and transmons. The controller comprises a qubit-phase-tracking direct digital synthesis (DDS) back end for coherent qubit control and a single-sideband (SSB) RF front end optimized for minimum leakage between the qubit channels. Fabricated in Intel 22-nm FinFET technology, it achieves a 48-dB SNR and 45-dB spurious-free dynamic range (SFDR) in a 1-GHz data bandwidth when operating at 3 K, thus enabling high-fidelity qubit control. By exploiting the on-chip 4096-instruction memory, the capability to translate quantum algorithms to microwave signals has been demonstrated by coherently controlling a spin qubit at both 14 and 18 GHz., OLD QCD/Charbon Lab, QuTech, QCD/Vandersypen Lab, Business Development, QCD/Scappucci Lab, QCD/Veldhorst Lab, QN/Vandersypen Lab, Electronics, (OLD)Applied Quantum Architectures

Manufacturing defects can cause faults in FinFET SRAMs. Of them, easy-to-detect (ETD) faults always cause incorrect behavior, and therefore are easily detected by applying sequences of write and read operations. However, hard-to-detect (HTD) faults may not cause incorrect behavior, only parametric deviations. Detection of these faults is of major importance as they may lead to test escapes. This paper proposes a new design-for-testability (DFT) scheme for FinFET SRAMs to detect such faults by creating a mismatch in the sense amplifier (SA). This mismatch, combined with the defect in the cell, will incorrectly bias the SA and cause incorrect read outputs. Furthermore, post-silicon calibration schemes can be used to avoid over-testing or test escapes caused by process variation effects. Compared to the state of the art, this scheme introduces negligible overheads in area and test time while it significantly improves fault coverage and reduces the number of test escapes., Computer Engineering, Quantum & Computer Engineering

In this paper, we develop an analytical PUF model based on a compact FinFET transistor model that calculates the PUF stability (i.e. PUF static noise margin (PSNM)) for FinFET based SRAMs. The model enables a quick design space exploration and may be used to identify critical parameters that affect the PSNM. The analytical model is validated with SPICE simulations. In our experiments, we analyze the impact of process variation, technology, and temperature on the PSNM. The results show that the analytical model matches very well with the simulation model. From the experiments we conclude the following: (1) nFET variations have a larger impact on the PSNM than pFET (1.5% higher PSNM in nFET variations than pFET variations at 25°C), (2) high performance SRAM cells are more skewed (1.3% higher PSNM) (3) the reproducibility increases with smaller technology nodes (0.8% PSNM increase from 20 to 14 nm) (4) increasing the temperature from-10°C to 120°C leads to a PSNM change of approximately 1.0% for an extreme nFET channel length., Accepted author manuscript, Computer Engineering, Quantum & Computer Engineering

Fin Field-Effect Transistor (FinFET) technology enables the continuous downscaling of Integrated Circuits (ICs), using the Complementary Metal-Oxide Semiconductor (CMOS) technology in accordance with the More Moore domain. Despite demonstrating improvements on short channel effect and overcoming the growing leakage problem of planar CMOS technology, the continuity of feature size miniaturization allowed by FinFETs tends to increase sensitivity to Single Event Upsets (SEUs) caused by ionizing particles, especially in blocks with higher transistor densities as Static Random-Access Memories (SRAMs). Variation during the manufacturing process has introduced different types of defects that directly affect the SRAM's reliability, such as weak resistive defects. As some of these defects may cause dynamic faults, which require more than one consecutive operation to sensitize the fault at the logic level, traditional test approaches may fail to detect them and test escapes can occur. These undetected faults associated with weak resistive defects may affect the FinFET -based SRAM reliability during the lifetime. In this context, this paper proposes to investigate the impact of ionizing particles on the reliability of FinFET -based SRAMs in the presence of weak resistive defects. Firstly, a TCAD model of a FinFET-based SRAM cell is proposed in order to allow the evaluation of the ionizing particle's impact. Then, SPICE simulations are performed considering the current pulse parameters obtained with TCAD. In this step, weak resistive defects are injected into the FinFET-based SRAM cell. Results show that weak defects may have either a positive or negative influence on the cell reliability against SEUs caused by ionizing particles., Computer Engineering, Quantum & Computer Engineering

In this paper, we present a new method to mitigate the effect of the charge collected by trigate FinFET devices after an ionizing particle impact. The method is based on the creation of an internal structure that generates an electrical field that drives the charge generated by the ion track out of the sensitive device terminals. This electrical field is generated with the insertion of complementary doped regions near the active region of the device. We analyze the influence of the distance of those regions to the device, their depth into the substrate and their doping concentration to determine the optimal implementation which minimizes the collected charge. The impact on the device performance in terms of leakage current, threshold voltage, maximum transconductance and subthreshold voltage swing has also been investigated. Our results show that the added structures introduce negligible effects in performance degradation and total leakage current, at the cost of a small increase in area. The simulations performed with technology computer-aided design numerical (TCAD) tools in 22nm bulk FinFET technology show that the amount of charge collected by the device terminals can be reduced up to 50% for a linear energy transfer (LET) of 60 MeV-cm2/mg., Peer Reviewed, Postprint (published version)

Herein, the electrical contact formation between the electrodes of the micro four‐point technique and a semiconducting sample is described. It is shown that the contact is formed in two stages: a voltage‐induced electrical contact formation, followed by a current‐induced decrease in contact resistance. Moreover, a method is proposed allowing for precise control of the final contact resistance. Finally, it is demonstrated that the contacting process is similar on 1D fin structures, where the demonstrated control of the electrical contact is needed while measuring on nanometer‐wide fins in arrays with a pitch smaller than the electrode contact size.

Пояснювальна записка дисертації за обсягом становить 73 сторінки, містить 31 рисунок та 4 таблиці. Використано 35 бібліографічних джерел. Актуальність теми. Одночасно зі зменшенням розмірів елементів інтегральних мікросхем вирішення теплових проблем пристроїв, що входять до їх складу набуває все більшої актуальності. Інтегральні схеми, що використовуються у військовій, автомобільній та атомній промисловості потребують високих робочих температур. Дослідження впливу різних факторів на самонагрів FinFET пристроїв є перспективним. Проте наразі чисельних досліджень процесів самонагріву в тривимірних транзисторах типу FinFET недостатньо. Зв'язок роботи з науковими програмами, планами, темами. Науково-дослідна робота за темою дисертації проводилася за власною ініціативою на кафедрі ФЕС НТУУ «КПІ імені Ігоря Сікорського». Мета дисертаційної роботи полягає в дослідженні впливу масштабування кремнієвого транзистору типу FinFET на потужність, що виділяється та зростання температури всередині пристрою. Досягнення мети передбачає вирішення таких задач: – Побудова структурної моделі FinFET; – Розрахунок розподілу потенціалу та вольт-амперних характеристик; – Дослідження процесу теплогенерації; – Побудова розподілу температури всередині пристрою; – Дослідження впливу геометрії на самонагрів транзистору; – Аналіз впливу нанорозмірних ефектів у каналі FinFET на процес самонагріву. Об’єктом дослідження є кремнієвий транзистор типу FinFET з розмірами 32 нм. Предметом дослідження є фактори, які впливають на процес самонагріву тривимірних транзисторів типу FinFET. Методи дослідження. Комп’ютерне моделювання структури FinFET. Побудова розподілу потенціалу шляхом чисельного розв’язання рівняння Пуассона. Одержання вольт-амперних характеристик згідно з моделлю дрейфу та дифузії. Чисельне моделювання процесу самонагріву FinFET. Були отримані наступні результати: 1. Проведено чисельне моделювання структури та процесів самонагріву FinFET транзистору за допомогою програмного пакету GTS Framewo, The thesis explanatory note contains 73 pages 4 tables and 31 figures with 35 names of bibliographic sources. The objective of this work is influence of FinFET-type silicon transistor parameters on its thermal characteristics. The purpose of this work is to investigate the influence of scaling of FinFET-type silicon transistor at power dissipation and temperature growth. The challenges are: to design FinFET structure; to calculate distribution of potential and transfer characteristics; to study heat generation; to calculate temperature distribution inside device; to investigate influence of geometry on self-heating of FinFET; to analyze influence of nanoscale effects in FinFET channel on its self-heating. The object of study is a silicon 32 nm FinFET device. The subject is an influence of different factors on self-heating of the FinFET type 3D transistor. Investigation methods. FinFET computer design. Numerical solution of Poisson equation. Obtaining of transfer characteristics according to drift-diffusion model. Numerical simulation of FinFET self-heating. Next results were received: 1. Numerical modelling of FinFET structure and process of self-heating using GTS Framework was conducted. 2. Influence of changes in device geometry at FinFET self-heating was investigated. Decreasing of device power dissipation due to geometry changes was demonstrated. 3. Increasing of heat flux density due to decreasing of device size was determined. 4. Influence of decreasing of device size on max temperature was studied. 5. Impact of nanoscale effects at FinFET self-heating was analyzed. Decreasing of channel heat conductivity leads to increasing of device max temperature. 6. Effect of channel heat conductivity decreasing on dissipated power was determined. Scientific novelty follows the definition of influence of geometry factor and heat conduction of nanoscale silicon at FinFET self-heating. The significance of the results. It was found that channel size decreasing allows reducin

Life on earth exists due to a delicate balance with nature, one that has been skewed in our favor since the industrial revolution. The growing population demands energy for homes, offices, portable devices and transportation. However, our reliance on natural gas/coal and petroleum to fulfill these requirements have led to an unprecedented increase in atmospheric CO2 levels that threaten our own existence. A paradigm shift in how we generate, store and monitor energy is needed, with green energy and sustainability paving a way forward. The advent of photovoltaics and Li-ion battery have given us the necessary tools to bring about this change, but continued research relies on a deeper understanding of the mechanisms involved and materials developed for each technology. As the materials chemistry, size of particles and nature of the interfaces become more complex, the need for nanoscale analysis has never been more aptly described. 3D tomographic measurements can provide a clear picture of the materials composition and interface properties, with atom probe tomography (APT) allowing a nanoscale chemical and spatial analysis. Herein, we use APT to enhance our understanding of the device mechanisms and core material properties for photovoltaics, Li-ion batteries and state-of-the-art semiconductor fins. Our understanding can help to build better structure-property relations by tying in nanoscale analysis with bulk properties that will ultimately lead to better design and development of energy devices across a broad range of technologies.

Compact model plays an important role in designing integrated circuits and serves as a bridge to share the information between foundries and circuit designers. Since various flavors of transistor architectures like FDSOIs and FinFETs are proposed to improve device performances, the accurate, fast, and robust compact models, which are capable of reproducing the very complicated transistor characteristics like transconductance, are urgently required. Novel device concept, such as tunnel FETs (TFETs) and negative capacitance FETs (NCFETs), needs new device modeling methodology and understanding of device physics. In addition to transistors, memory device like magnetic tunnel junction (MTJ) compact model is also crucial for circuit designs. This dissertation presented the advanced research on compact models for the state-of-the art transistor and memory technologies: FDSOIs, FinFETs, TFETs, NCFETs, and MTJs.Due to the limitations in the aggressively scaled planar transistors, the devices with good electrostatic control are discussed and modeled into the industry standard model - BSIM-IMG for FDSOIs and BSIM-CMG for multi-gate FETs. Although the dynamic back-gate bias change help reduce the static power in FDSOIs, the leakages, overlap capacitance, and carrier transport are thus showing back-gate bias-dependence. The enhanced gate-related leakage, overlap capacitance, and mobility compact models are validated against the silicon data and incorporated into BSIM-IMG. The leakages through subsurface path and source-to-drain direct tunneling due to extremely short channel are also included in this work, which are in excellent agreement with the technology computer-aided design (TCAD) and atomistic simulations. The computationally efficiency of these models are the key solutions for evaluating the circuit performance of future technology nodes.Two paradigms of steep subthreshold slope transistors - TFETs and NCFETs as the promising candidates for future Internet of Things (Io

Until 2003, the semiconductor industry followed Dennard scaling rules to improve complementary metal-oxide-semiconductor (CMOS) transistor performance. However, performance gains with further reductions in transistor gate length are limited by physical effects that do not scale commensurately with device dimensions: short-channel effects (SCE) due to gate-leakage-limited gate-oxide thickness scaling, channel mobility degradation due to enhanced vertical electric fields, increased parasitic resistances due to reductions in source/drain (S/D) contact area, and increased variability in transistor performance due to random dopant fluctuation (RDF) effects and gate work function variations (WFV). These emerging scaling issues, together with increased process complexity and cost, pose severe challenges to maintaining the exponential scaling of transistor dimensions. This dissertation discusses the benefits of oxygen-insertion (OI) technology, a CMOS performance booster, for overcoming these challenges. The benefit of OI technology to mitigate the increase in sheet resistance ($R_{sh}$) with decreasing junction depth ($X_J$) for ultra-shallow-junctions (USJs) relevant for deep-sub-micron planar CMOS transistors is assessed through the fabrication of $R_{sh}$ test structures, electrical characterization, and technology computer-aided design (TCAD) simulations. Experimental and secondary ion mass spectroscopy (SIMS) analyses indicate that OI technology can facilitate low-resistivity USJ formation by reducing $R_{sh}$ and $X_J$ due to retarded transient-enhanced-diffusion (TED) effects and enhanced dopant retention during post-implantation thermal annealing. It is also shown that a low-temperature-oxide (LTO) capping can increase $R_{sh}$ unfavorably due to lower dopant activation levels, which can be alleviated by OI technology. This dissertation extends the evaluation of OI technology to advanced FinFET technology, targeting 7/8-nm low power technology node. A bulk-Si FinFE

Standard low power design utilizes a variety of approaches for supply and threshold control to reduce dynamic and idle power. At a very early stage of the design cycle, the Vdd and Vth values are estimated, based on the power budget, and then used to scale the delay and estimate the design performance. Furthermore, process variation in sub-20 nm feature technologies introduces a substantial impact on speed and power. Thus, the impact of such variation on the scaled delay has to also be considered in the performance estimation. In this paper, we propose a system-level model to estimate this delay, taking into consideration voltage scaling under within-die process variation for both planar and FinFET CMOS transistors in the sub-20 nm regime. The model is simple, has acceptable accuracy and is particularly useful for architectural-level simulations for low-power design exploration at an early stage in the design space exploration. The proposed model estimates the delay in different supply voltage and threshold voltage ranges. The model uses a modified alpha-power equation to measure the delay of the critical path of a computational logic core. The targeted technology nodes are 14 nm, 10 nm, and 7 nm for FinFETs, and 22 nm, and 16 nm for planar CMOS. Within-die process variation is assumed to be lumped in with the threshold voltage and the transistor channel length and width to simplify its impact on delay. For the given technology nodes, the average percentage error numbers of theproposed delay equation compared to hSpice are between 0.5% to 14%., Computer Engineering, Quantum & Computer Engineering

Hard-to-detect faults such as weak and random faults in FinFET SRAMs represent an important challenge for manufacturing testing in scaled technologies, as they may lead to test escapes. This paper proposes a Design-for-Testability (DFT) scheme able to detect such faults by monitoring the bitline swing of FinFET memories. Using only five operations per cell, we are able to detect defects that cause deterministic, random, and weak faults. Compared to the state of the art, this leads to an improved detection capability at reduced area overhead., Accepted author manuscript, Computer Engineering, Quantum & Computer Engineering

Advanced Encryption Standard (AES) is the widely used technique in critical cyber security applications. In AES architecture S-box is the most important block. However, the power consumed by     S-box is 75% of the total AES design. The  S-box is also prone to Differential Power Analysis (DPA) attack which is one of the most threatening types of attacks in cryptographic systems. In this paper, a    three-stage positive polarity Reed-Muller (PPRM) S-box is implemented with 45nm FinFET using Efficient Charge Recovery Logic (ECRL) to reduce power consumption. The simulation results indicate up to 66% power savings for FinFET based S-box as compared to CMOS design. Further, the FinFET ECRL 8-bit    S-box circuit is evaluated for transitional energy fluctuations and peak current traces to compare its resistance against side-channel attacks. The lower energy variations and uniform current trace exhibit the improved security performance of the circuit to withstand DPA and Differential Electromagnetic Radiation Attacks (DEMA).

Hot-carrier effect and oxide reliability of CMOS T-FinFET with 2.1nm-thick gate-SiO2 were investigated. It was found that hot-carrier immunity improves as the T-FinFET fin width (body thickness) decreases, which facilitates gate-length scaling, while it is degraded at elevated temperature due to the self-heating effect. High values of QBD are achieved for devices with very small gate area. A post-fin-etch hydrogen anneal is helpful for improving hot-carrier immunity and QBD. © 2018 by TechConnect. All rights reserved.

With the advent of the slowdown in DRAM capacitor scaling [1] and the increased reliability problems of traditional 6T SRAM memories [2], industry and academia have looked for alternative memory cells. Among those, gain- cells have attracted significant attention due to their smaller size (compared to SRAM) and non-destructive read operation (compared to DRAM) as well as considerable low power and reasonable robustness. This paper first summarizes the available evidences of SRAM and eDRAM in commercial and test chips. Then, it analyzes the performance, reliability and scaling of eDRAM gain-cells in 10 and 7 nm FinFET technology; as well as above and below VT (i.e. sub-threshold)., Peer Reviewed, Postprint (author's final draft)

Sub-threshold circuits (sub-V T) are a promising alternative in the implementation of low power electronics. The implementation of gain-cell embedded DRAMs (eDRAMs) based on FinFET devices requires a careful design to achieve the maximum cell performance (i.e., retention time, access time, and energy consumption) suitable for the sub-V T operating level. In this work, we show that asymmetrically resizing the memory cell (i.e., the channel length of the write access transistor and the width of the rest of the devices) results in a 3.5× increase in retention time when compared to the nominal case while reducing area, as well. In terms of reliability (e.g., variability and soft errors), the resizing also improves the cell robustness (50% and 1.9×, respectively) when the cells are operated at sub-V T level., Peer Reviewed, Postprint (published version)

We summarize most of our studies focused on the main reliability issues that can threat the gain-cells eDRAM behavior when it is simulated at the nano-metric device range has been collected in this review. So, to outperform their memory cell counterparts, we explored different technological proposals and operational regimes where it can be located. The best memory cell performance is observed for the 3T1D-eDRAM cell when it is based on FinFET devices. Both device variability and SEU appear as key reliability issues for memory cells at sub-22nm technology node., Peer Reviewed, Postprint (author's final draft)

This paper demonstrates the development of a methodology using the micro four-point probe (mu 4PP) technique to electrically characterize single nanometer-wide fins arranged in dense arrays. We show that through the concept of carefully controlling the electrical contact formation process, the electrical measurement can be confined to one individual fin although the used measurement electrodes physically contact more than one fin. We demonstrate that we can precisely measure the resistance of individual ca. 20 nm wide fins and that we can correlate the measured variations in fin resistance with variations in their nanometric width. Due to the demonstrated high precision of the technique, this opens the prospect for the use of mu 4PP in electrical critical dimension metrology.

In this work, optimization of selective epitaxy growth (SEG) of SiGe layers on source/drain (S/D) areas in 14nm node FinFETs with high-k & metal gate has been presented. The Ge content in epilayers was in range of 30%-40% with boron concentration of 1-3 × 1020 cm-3. The strain distribution in the transistor structure due to SiGe as stressor material in S/D was simulated and these results were used as feedback to design the layer profile. The epitaxy parameters were optimized to improve the layer quality and strain amount of SiGe layers. The in-situ cleaning of Si fins was crucial to grow high quality layers and a series of experiments were performed in range of 760-825 °C. The results demonstrated that the thermal budget has to be within 780-800 °C in order to remove the native oxide but also to avoid any harm to the shape of Si fins. The Ge content in SiGe layers was directly determined from the misfit parameters obtained from reciprocal space mappings using synchrotron radiation. Atomic layer deposition (ALD) technique was used to deposit HfO2 as high-k dielectric and B-doped W layer as metal gate to fill the gate trench. This type of ALD metal gate has decent growth rate, low resistivity and excellent capability to fill the gate trench with high aspect-ratio. Finally, the electrical characteristics of fabricated FinFETs were demonstrated and discussed., QC 20170613

The semiconductor industry has seen tremendous progress over the last few decades with continuous reduction in transistor size to improve device performance. Miniaturization of devices has led to changes in the dopants and dielectric layers incorporated. As the gradual shift from two-dimensional metal-oxide semiconductor field-effect transistor to three-dimensional (3D) field-effect transistors (finFETs) occurred, it has become imperative to understand compositional variability with nanoscale spatial resolution. Compositional changes can affect device performance primarily through fluctuations in threshold voltage and channel current density. Traditional techniques such as scanning electron microscope and focused ion beam no longer provide the required resolution to probe the physical structure and chemical composition of individual fins. Hence advanced multimodal characterization approaches are required to better understand electronic devices. Herein, we report the study of 14 nm commercial finFETs using atom probe tomography (APT) and scanning transmission electron microscopy-energy-dispersive X-ray spectroscopy (STEM-EDS). Complimentary compositional maps were obtained using both techniques with analysis of the gate dielectrics and silicon fin. APT additionally provided 3D information and allowed analysis of the distribution of low atomic number dopant elements (e.g., boron), which are elusive when using STEM-EDS.

In this thesis, InGaAs fins with vertical sidewalls consisting of {110} facets were epitaxially grown on InP(111)B substrates using metalorganic vapor phase epitaxy. A lithography patterned hydrogen silsesquixane growth mask was used to promote the formation of vertical {110} facets during the growth. The relative growth rate of the {111B} and {110} facets was controlled by the input V/III ratio in the gas phase. It was found that for low V/III ratios, high InGaAs fins with minimal mask overgrowth could be grown. Facet selective growth of InGaAs fins on InP(111)B can thus be used to fabricate the channel in modern fin field-effect transistors (FinFETs). Prior to the growth of InGaAs fins, the chemical composition of epitaxially grown InGaAs films on different InP substrates was measured using reciprocal space mapping. The purpose of this was to calibrate the InGaAs growth in terms of chemical composition on various crystal facets. Several thin InGaAs films were grown at 600 C using trimethyl gallium, trimethyl indium, and arsine. The results revealed that the chemical composition of InGaAs on InP(111)B, InP(110), and InP(001) differed considerably when grown during identical conditions. It was found that thin InGaAs films of good crystal quality could be grown on InP(111)B and InP(001) during these conditions. The growth on InP(110) during the same conditions resulted in relaxed gallium rich InGaAs films., Moderna elektronikprylar så som mobiltelefoner, datorer och surfplattor innehåller flera integrerade kretsar vars uppgifter varierar. En dator har till exempel en viss integrerad krets, kallad processor, vars uppgift är att uföra beräkningar och att driva operativsystemet. Samma dator innehåller även ytterliggare integrerade kretsar vars uppgifter kan vara att behandla grafik, ljud och trådlös kommunikation. Det behövs alltså många olika kretsar för att en dator ska fungera. Vad alla dessa kretsar har gemensamt är att de innehåller flera miljoner (ibland miljarder) elektriska komponenter som kan bindas samman på en yta lika liten som en enkrona. Dessa elektriska komponenter kallas transistorer och kan användas för att förstärka eller för att styra elektriska signaler. Transistorns egenskaper tillåter den att styra små elektriska signaler baserat på en styrsignal. Man kan exempelvis stänga av eller sätta igång en transistor med hjälp av en styrsignal och detta kan göras flera miljarder gånger på en enda sekund! Man kan därför skapa väldigt stora nätverk av miljardtals sammankopplade transistorer på väldigt små ytor. Samspelet mellan de sammankopplade transistorerna som stängs av eller sätts igång flera miljarder gånger per sekund kan användas för att utföra beräkningar. Beräkningar i datorvärlden utförs med hjälp av det binära talsystemet som endast inehåller ettor och nollor. Transistorernas uppgift är därför att representera långa kombinationer av ettor och nollor som sedan kan omvandlas till det decimala talsystemet, det talsystem som människor är vana vid. En nolla i datorvärlden representeras av en avstängd transistor medan en etta representeras av en transistor som är igång. Ett nätverk av transistorer kan därför utföra tunga beräkningar väldigt snabbt eftersom varje transistor i nätverket kan stängas av och sättas igång flera miljarder gånger per sekund. Okej visst, men hur kan så många transistorer få plats på en så liten yta? Jo, tricket är att man tillverka

The scope of this project is to develop a base methodology for clock tree synthesis that can improve the base results regarding the clock structure. The analysis of results will be done with a Quality of Results sets of metrics and by analysing the physical structure of the clock. The analysis has been performed on three blocks with different physical characteristics to achieve a transversal solution. The initial tests performed have been focused on configuration options of the EDA tool used but were disregarded. The main tests upon this thesis is based are referred to the clock physical structure such as fanout constraints, slew constraints and clock cell selection. One of the main results obtained is the importance of the layout of the block to set up the optimal constraints, limiting the transversal solution approach. It is as well an important point considering the internal algorithms followed by the tool.

This paper explores the feasibility, in terms of performance and reliability, of gain-cell embedded DRAM (eDRAM) to be operative at sub-threshold range, when they are implemented with 10 nm FinFET devices. The use of individual transistor resizing in order to achieve better cell performance (i.e. retention time, access time, and energy consumption) at the sub-VT operating level is studied. In this scenario, asymmetrically resizing the memory cell, since we modify the channel length of the write access transistor and the width of the rest of the devices in the eDRAM cell, entails a 3.5x increase in retention time as compared to the nominal case and with smaller area overhead. Moreover, such a resizing significantly improves reliability against variability and soft errors (50% and 1.9x, respectively) when the cells are operated at sub-VT level., Peer Reviewed, Postprint (author's final draft)

Plasma doping ion implantation (PLAD) is becoming increasingly important in the manufacture of advanced semiconductor device structures but a fundamental understanding of PLAD is complicated. A model of PLAD into planar substrates has been constructed using the one dimensional computer code TRIDYN to predict collision cascades and hence substrate compositional changes during implantation. Medium Energy Ion Scattering (MEIS) measurements of dopant profiles in PLAD processed samples were used to calibrate the input ion and neutral fluxes to the model. Rules could then be proposed for how post implant profiles should be modified by a cleaning step. This learning was applied to a three dimensional TRI3DYN based model for PLAD implants into FinFET like structures. Comparison of the model to dopant profile measurements made by time of flight (TOF)-MEIS revealed the angular distributions of neutral species and doping mechanisms acting in three dimensional structures.

Short channel effects, such as DIBL are compared for SOI-FinFETs with different silicon body geometries. The original device considered was straight without narrowing at the top and a set of devices that exhibit the mentioned narrowing, up to the extreme case where the top of the gate has no surface and so the body cross-section is essentially a triangle. We have studied five different variations from the original geometry of a 25 nm gate length SOI-FinFET device with 1.5 nm thick oxide layer. The P-type channel had a doping concentration of 1015 cm−3 and n-type S/D areas are doped at concentrations of 1020 cm−3 . The silicon body of the device accordingly had a height of 30 nm and a width of 12 nm. Simulation results show the source-drain barrier decreasing with increasing the upper body thickness. The DIBL effect of the considered FinFETs depends on upper body thickness, tending to increase with thicker upper body widths. Results of a comparison of two devices with different shapes but with the same cross-sectional area shows the relationship mainly depends on the shape rather than the cross-section area of the device body

A complete mapping of 14 nm FinFETs performance over 200 mm wafers was performed and the pattern dependency of SiGe selective growth was calculated using an empirical kinetic molecule model for the reactant precursors. The transistor structures were analyzed by conventional characterization tools and their performance was simulated by considering the process related variations. The applied model presents for the first time a powerful tool for transistor community to predict the SiGe profile and strain modulating over a processed wafer, independent of wafer size., QC 20161014

In this study, the process integration of SiGe selective epitaxy on source/drain regions, for 16/14 nm nodes FinFET with high-k & metal gate has been presented. Selectively grown Si1-xGex (0.35 <= x <= 0.40) with boron concentration of 1 x 10(20) cm(-3) was used to elevate the source/drain of the transistors. The epi-quality, layer profile and strain amount of the selectively grown SiGe layers were also investigated by means of various characterizations. A series of prebaking experiments were performed for temperatures ranging from 740 to 825 degrees C in order to in situ clean the Si fins prior to the epitaxy. The results showed that the thermal budget needs to be limited to 780-800 degrees C in order to avoid any damages to the shape of Si fins but to remove the native oxide effectively which is essential for high epitaxial quality. The Ge content in SiGe layers on Si fins was determined from the strain measured directly by reciprocal space mappings using synchrotron radiation. Atomic layer deposition technique was applied to fill the gate trench with W using WF6 and B2H6 precursors. By such an AID approach, decent growth rate, low resistivity and excellent gap filling capability of W in pretty high aspect-ratio gate trench was realized. The as-fabricated FinFETs demonstrated decent electrical characteristics., QC 20160926

2013年度～2015年度 科学研究費助成事業(基盤研究(B))研究成果報告書, publisher

This paper developed a full three-dimensional (3-D) statistical simulation method to investigate Fin-width Line Edge Roughness (LER) effect on the FinFETs performance. The line edge roughness is introduced by Matlab program, and then the intrinsic parameter fluctuations at fixed LER parameters are studied in carefully designed simulation experiments. The result shows that Fin-width LER causes a dramatic shift and fluctuations in threshold voltage. The simulation results also imply that the velocity saturation effect may come into effect even under low drain voltage due to LER effect.