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Structural and electrical properties of ALD-grown 5 and 7 nm-thick Al2O3 layers before and after implantation of Ge ions (1 keV, 0.5–1 x 1016 cm-2) and thermal annealing at temperatures in the 700–1050°C range are reported. Transmission Electron Microscopy reveals the development of a 1 nm-thick SiO2-rich layer at the Al2O3/Si substrate interface as well as the formation of Ge nanocrystals with a mean diameter of ca. 5 nm inside the implanted Al2O3 layers after annealing at 800 °C for 20 min. Electrical measurements performed on metal–insulator–semiconductor capacitors using Ge-implanted and annealed Al2O3 layers reveal charge storage at low-electric fields mainly due to location of the Ge nanocrystals at a tunnelling distance from the substrate and their spatial dispersion inside the Al2O3 layers.

Structural and electrical properties of ALD-grown 5 and 7 nm-thick Al2O3 layers before and after implantation of Ge ions (1 keV, 0.5–1 x 1016 cm-2) and thermal annealing at temperatures in the 700–1050°C range are reported. Transmission Electron Microscopy reveals the development of a 1 nm-thick SiO2-rich layer at the Al2O3/Si substrate interface as well as the formation of Ge nanocrystals with a mean diameter of ca. 5 nm inside the implanted Al2O3 layers after annealing at 800 °C for 20 min. Electrical measurements performed on metal–insulator–semiconductor capacitors using Ge-implanted and annealed Al2O3 layers reveal charge storage at low-electric fields mainly due to location of the Ge nanocrystals at a tunnelling distance from the substrate and their spatial dispersion inside the Al2O3 layers.

Structural and electrical properties of ALD-grown 5 and 7 nm-thick Al2O3 layers before and after implantation of Ge ions (1 keV, 0.5–1 x 1016 cm-2) and thermal annealing at temperatures in the 700–1050°C range are reported. Transmission Electron Microscopy reveals the development of a 1 nm-thick SiO2-rich layer at the Al2O3/Si substrate interface as well as the formation of Ge nanocrystals with a mean diameter of ca. 5 nm inside the implanted Al2O3 layers after annealing at 800 °C for 20 min. Electrical measurements performed on metal–insulator–semiconductor capacitors using Ge-implanted and annealed Al2O3 layers reveal charge storage at low-electric fields mainly due to location of the Ge nanocrystals at a tunnelling distance from the substrate and their spatial dispersion inside the Al2O3 layers.

Nanocrystal memories are attractive candidate for the development of non volatile memory devices for deep submicron technologies. In a nanocrystal memory device, a 2D network of isolated nanocrystals is buried in the gate dielectric of a MOS and replaces the classical polysilicon layer used in floating gate (flash) memories. Recently, we have demonstrated a route to fabricate these devices at low cost by using ultra low energy ion implantation. Obviously, all the electrical characteristics of the device depend on the characteristics of the nanocrystal population (sizes and densities) but also on their exact location with respect to the gate and channel of the MOS transistor. It is the goal of this paper to report on the main materials science aspects of the fabrication of 2D arrays of Si nanocrystals in thin SiO2 layers and at tunable distances from their SiO2/interfaces.

Nanocrystal memories are attractive candidate for the development of non volatile memory devices for deep submicron technologies. In a nanocrystal memory device, a 2D network of isolated nanocrystals is buried in the gate dielectric of a MOS and replaces the classical polysilicon layer used in floating gate (flash) memories. Recently, we have demonstrated a route to fabricate these devices at low cost by using ultra low energy ion implantation. Obviously, all the electrical characteristics of the device depend on the characteristics of the nanocrystal population (sizes and densities) but also on their exact location with respect to the gate and channel of the MOS transistor. It is the goal of this paper to report on the main materials science aspects of the fabrication of 2D arrays of Si nanocrystals in thin SiO2 layers and at tunable distances from their SiO2/interfaces.

In silicon nanocrystal (nc) based metal-oxide-semiconductor (MOS) memory structures a fine control of the Si nc location in the gate oxide is required for the pinpointing of optimal device architectures. In this work, we show how to manipulate and control the depth-position, size and surface density of two dimensional (2D) arrays of Si ncs embedded in thin (<10 nm) SiO2 layers, fabricated by ultra-low-energy (typically 1 keV) ion implantation and subsequent annealing. Particular emphasis is placed upon the influence of implantation and annealing conditions and oxide thickness on the nanocrystal characteristics (e.g. size, density) and the charge storage properties of associated MOS structures. Structural investigation is performed by using specific characterization methods including Fresnel imaging for the measurement of the injection distance between the substrate and the nc band, as well as spatially resolved Electron Energy Loss Spectroscopy using the spectrum-imaging mode of a Scanning Transmission Electron Microscope to evaluate the size distribution and density of the ncs.

An abstract is not available, please contact the authors.

An abstract is not available, please contact the authors.

Scalability and performance of current flash memories can be improved substantially by novel devices based on Multi-Dot Floating Gate MOSFETs. The multi-dot layer in the very thin gate oxide can be fabricated CMOS-compatibly by ion beam synthesis (IBS). Here, we present both experimental and theoretical studies on IBS of multi-dot layers consisting of Si nanocrystals (NCs). The NCs are produced by ultra low energy Si ion implantation, which causes a high Si supersaturation in the shallow implantation region. During post-implantation annealing, this su-persaturation leads to phase separation of the excess Si from the SiO₂. Till now, the study of this phase separation suffered from the weak z contrast between Si and SiO₂ phases in Transmission Electron Microscopy (TEM). Here, this imaging problem is solved by Energy Filtered Scanning Transmission Electron Microscopy (EFSTEM). Additionally, kinetic lattice Monte Carlo simula-tions of Si phase separation have been performed and compared with EFSTEM images. It has been predicted theoretically that the morphology of the multi-dot Si floating gate changes with increasing ion fluence from isolated, spherical NCs to percolated spinodal Si pattern. These pat-tern agree remarkably with EFSTEM images. However, the predicted fluence for spinodal pattern is lower than the experimental one. Because oxidants of the ambient atmosphere penetrate into the as-implanted SiO₂, a substantial fraction of the implanted Si is lost due to oxidation.

An abstract is not available, please contact the authors.

An abstract is not available, please contact the authors.

Studies on the ion beam synthesis of narrow Si nanocrystal (NC) layers in thin SiO2 films are presented. Very low-energy Si+ implantation into gate oxides for MOS transistors followed by thermal annealing allows for the fabrication of novel Si NC floating gate based non-volatile charge storage devices. Small and isolated Si NCs at high density are required to obtain a large threshold voltage shift of the memory transistor. However, former work shows that the characterization of the Si NCs embedded in SiO2 by conventional Transmission Electron Microscopy (TEM) is difficult. It requires careful con-siderations and special imaging conditions [1] due to the weak contrast be-tween Si and SiO2 . In this contribution, Energy Filtered Scanning Transmission Electron Micros-copy (EFSTEM) investigations on the morphology of phase separated Si in SiO2 are presented, which overcome the contrast limitations of the conven-tional TEM. Furthermore, a comparison of the observed Si pattern with pre-dictions of kinetic lattice Monte Carlo (MC) simulations [2] is performed. The Si precipitates were synthesized by 1 keV Si+ implantation into 10 nm thick SiO2 and by furnace annealing in N2 (or N2 + O2). Varying fluences from 5E15 to 2E16 Si+ cm-2 were used in order to adjust the Si excess in the SiO2. For these conditions, dynamical binary collision simulations (TRIDYN) of high-fluence implantation were combined with kinetic Monte Carlo simula-tions of NC formation by phase separations. For low Si excess, NCs are pre-dicted to form by nucleation, growth and Ostwald ripening. On the other hand, at high Si excess, phase separation proceeds via spinodal decomposition, were elongated NCs are found in our computer experiment. At even higher flu-ences, structural percolation occurs and a random connected Si mesh forms. Thus, the morphology of the phase separated Si changes with increasing ion fluence from isolated, spherical NCs to percolated structures as observed by EFSTEM. The pattern of the

Studies on the ion beam synthesis of narrow Si nanocrystal (NC) layers in thin SiO2 films are presented. Very low-energy Si+ implantation into gate oxides for MOS transistors followed by thermal annealing allows for the fabrication of novel Si NC floating gate based non-volatile charge storage devices. Small and isolated Si NCs at high density are required to obtain a large threshold voltage shift of the memory transistor. However, former work shows that the characterization of the Si NCs embedded in SiO2 by conventional Transmission Electron Microscopy (TEM) is difficult. It requires careful con-siderations and special imaging conditions [1] due to the weak contrast be-tween Si and SiO2 . In this contribution, Energy Filtered Scanning Transmission Electron Micros-copy (EFSTEM) investigations on the morphology of phase separated Si in SiO2 are presented, which overcome the contrast limitations of the conven-tional TEM. Furthermore, a comparison of the observed Si pattern with pre-dictions of kinetic lattice Monte Carlo (MC) simulations [2] is performed. The Si precipitates were synthesized by 1 keV Si+ implantation into 10 nm thick SiO2 and by furnace annealing in N2 (or N2 + O2). Varying fluences from 5E15 to 2E16 Si+ cm-2 were used in order to adjust the Si excess in the SiO2. For these conditions, dynamical binary collision simulations (TRIDYN) of high-fluence implantation were combined with kinetic Monte Carlo simula-tions of NC formation by phase separations. For low Si excess, NCs are pre-dicted to form by nucleation, growth and Ostwald ripening. On the other hand, at high Si excess, phase separation proceeds via spinodal decomposition, were elongated NCs are found in our computer experiment. At even higher flu-ences, structural percolation occurs and a random connected Si mesh forms. Thus, the morphology of the phase separated Si changes with increasing ion fluence from isolated, spherical NCs to percolated structures as observed by EFSTEM. The pattern of the