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The market and the applications of micro-electromechanical systems (MEMS)-based microphones have been in continuous growth over the last decades. This article presents a promising acoustic-sensing technology that mixes the consolidated MEMS technology with an innovative optical transduction technique of acoustic signals. The proposed method allows to significantly reduce the intrinsic noise of the system and to increase its signal-to-noise ratio (SNR). The designed digital optical microphone reaches an SNR of 71.6 dBA in a 5 x 5 x 2 mm (3) package with an output sensitivity of - 21 dBFS/Pa. This article describes each section of the system-in-package (SiP) microphone, starting from the physics behind the transduction mechanism, covering the application-specified integrated circuit (ASIC) and package design, and the optical stack structure. A final analysis of the obtained experimental results is provided and compared with the state-of-art reported in the literature.

In this paper, a Supply Embedded Communication (SEC) transceiver for automotive networks is proposed. In an SEC approach, power supply and communication take place on the same differential bus and thus the number of required cables is drastically reduced, leading to space, raw material consumption, and cost advantages. The proposed transceiver is realized in 180nm SOI CMOS technology and is capable of implementing 2Mbps high-speed networks. In addition to proving nominal transient operation, some critical aspects for an automotive application are analyzed. Electromagnetic compatibility (EMC) is evaluated by conducting emission tests, and finally, the robustness to external disturbances is tested by direct power injection (DPI) tests.

This paper presents a fully integrated 55nm CMOS Voltage Reference Generator for audio interface. The reference is made up of a Bandgap voltage reference and a Low-Dropout regulator. The topology chosen for the bandgap is a current mode bandgap with adjustable output resistor. This guarantees a reference voltage of less than 1.2V thanks to the sum of two currents instead of two voltages. A double loop was chosen for the LDO regulator to ensure rapid transient response. For BG, current consumption is less than 5uA, DC PSR lower than -60dB and a temperature coefficient around 70ppm/°C. The LDO has a PSR of around -70dB in the audio band ([20, 20K]Hz) and a current consumption of around 10uA and 5uA for Normal Mode and Low Power mode respectively.

A low dropout regulator (LDO) is designed in 55nm CMOS technology. It is targeted for high-end audio applications, which present continuous-time as well as switched-capacitor building blocks. A multiple loop capacitor-less structure is pro- posed to cope with both high power supply rejection ratio (PSRR) and fast transient response. In particular, a folded flipped voltage follower (FFVF) output buffer presents a fast inner loop, needed to detach the error amplifier (EA) from the load capacitor (CL) and drive this latter under fast transients. A variable resistance and adaptive biasing are developed to guarantee stability under all load conditions, including IL = 0. Moreover, a slower high- gain loop is designed to set the output potential Vout, further reducing the output impedance and improving the PSRR, line and load regulation. The proposed LDO is implemented using IO high threshold transistors and provides an output voltage Vout = 1 V from a 1.2 V 10% supply with a minimum possible dropout (V min drop ) of 80 mV. It achieves a worst-case low-frequency PSRR of -76.2 dB under Montecarlo simulations (MC) and a recovery time of 142 ns when a load spike of 800 ?A is applied. Line and load regulation are 0.001 mV/V and 0.007 mV/mA. Moreover, the quiescent current (Iq ) is less than 20 ?A at maximum IL. © 2024 IEEE.

This paper presents the complete transistor-level design of a Low-Noise-Amplifier (LNA) in CMOS 28 nm bulk technology for sensing the weak extracellular neuro-potentials signals in Electrolyte-Oxide-MOS (EOMOS) Brain-Chip Interfaces. The proposed LNA adopts an efficient pseudo-resistor topology that allow to synthesize a stable resistance (in the tens of {G} order) without any external calibration. The LNA has 2.4 Hz minimum passband frequency performing 7.8 {V}_{RMS and 8.8mu {V}_{RMS input-referred noise power at 1 Hz - 300 Hz (Local Field Potential) and 300 Hz-5 kHz (Action Potentials) bandwidth, respectively. The device consumes 2.4 {W} power and has been designed in 28 nm CMOS technology.

This work presents the design and experimental validation of a low-noise amplifier based on a ultra-low-noise JFET for noise characterization of materials samples for neural interfaces. The JFET LNA amplifies the sample noise power by 46 dB well above a lock-in amplifier noise floor, used as spectrum analyzer for noise characterization. The LNA exploits the high gm and low flicker corner frequency of JFETs to achieve 0.15 dB noise figure. The JFET LNA has been characterized in terms of frequency response and noise power spectrum and experimentally validated by characterizing the noise spectrum of a platinum silicide (PtSi) sample.

Ionoacoustic detectors sense the weak signal emitted by the fast energy deposition of a proton beam through the energy absorber and exploit this detected signal to spatially measure the beam penetration depth or range, with promising application in hadron therapy treatment monitoring. However, clinical scenarios exhibit very weak acoustic signal power (tens of mPa) in 10 kHz - 1 MHz bandwidth. Therefore, it is of fundamental importance that the front-end amplifiers operate at very low noise levels (few nV/v Hz of in-band noise power spectral density) to minimize the degradation of the Signal-to-Noise Ratio (SNR). The Low-Noise-Amplifier (LNA) proposed in this paper operates in such a critical scenario, exploiting an advanced and dc-stable pseudo-resistor implementation to minimize noise power, achieving 0.26 dB of Noise Figure. The LNA has been designed in 28 nm CMOS technology, has a passband gain of 30 dB, an integrated noise power in the ionoacoustic bandwidth of 7.5 mu V-RMS and 2.4 mW power consumption.

This paper presents an ultra-low power, area-efficient 4-channel front-end electronics for Monitored Drift Tubes (MDT) at Atlas Experiment. The proposed design is composed by low-noise Charge Sensitive Preamplffier (for charge-to-voltage conversion), a continuous-time Shaper/filter for Bipolar Time-Domain Pulses feeding a dynamic (no-clocked) Comparator (for voltage to time conversion). The system is designed to detect an input charge in the range of 5-100fC. The peaking time of Analog channel is 14.6 ns and exhibits a sensitivity of 8 mV/fC. The design has a single mode of operation, time-over-threshold (ToT). At the output the ToT encoding of input charge is provided in low-voltage differential signal, for connecting with TDC board, along with digital CMOS level signal. The design is operated from a single 1.2 V supply voltage. The chip is realized in 65 nm CMOS technology and has a total area occupancy of 4 mm2.

This study presents the first in depth characterization of deep cryogenic electrical behavior of a commercial 16 nm CMOS FinFET technology. This technology is well suited for a broad range of applications, including quantum computing, quantum sensing, and quantum communications. Cryogenic DC measurements and physical parameters extraction were carried out on this commercial FinFET technology, operating at room temperature, i.e., 300 K, and down to 2.95 K for different device types and geometries. This represents the main step towards cryogenic compact modeling and optimization of three-dimensional CMOS structures for quantum computations.

Custom integrated DC-DC converters are frequently used to power system-on-chip architectures for achieving high-quality voltage regulation at the best possible efficiency. However, high-level models of such converters are usually incompatible with analog simulators and require the designer to re-assemble the circuit in the final design environment to verify the design with real transistor models. This process is both time consuming and error-prone. This paper presents a library of parameterizable, high-level macro-models for DC-DC converters, consisting of custom Verilog-A modules and cells from the standard libraries. The macro-models are compatible with analog simulators and offer a significant amount of flexibility to the designer.

This work presents the experimental results of a wavelet transform-based denoising algorithm to improve the signal-to-noise ratio (SNR) in Proton Sound Detectors (ProSDs). ProSDs are thermoacoustic detectors that exploit the acoustic signal generated by pulsed proton beams in energy absorbers to locate energy deposition with sub-millimeter precision, with interesting applications in beam monitoring during oncological hadron therapy treatments. This work shows how the application of a denoising algorithm allows to improve the signal-to-noise ratio and reduce the extra-dose necessary to characterize the beam. The algorithm was validated with the thermoacoustic signal generated by a proton beam at 20 MeV, where it allowed to increase the SNR by 19 dB and decrease the dose necessary to characterize the beam by a factor of 80 compared to the state of the art.

This paper presents a dual-mode, multi-bit, second-order oversampling ADC, which can be configured into Sigma-Delta (SD) mode or Incremental (I) mode for interfacing a single or multiple sensors in multi-sensor platforms for automotive applications. Implemented in a 130-nm CMOS technology, the proposed ADC uses only 0.4 m devices and operates at 2.5-V supply in order to be connected to high-voltage sensors, at the cost of intrinsic lower efficiency. The device achieves a maximum SNDR of 63.0 dB and 56.4 dB in the two modes, respectively, with a bandwidth of 2.1 MHz. By reducing the bandwidth to 1.25 MHz in SD-mode a SNR of 73.2 dB is achieved. In both operating modes, the ADC is clocked at 80 MHz, consuming 2.6 mA.

In this paper a low-power, low-noise interface for Micro Electro-Mechanical System (MEMS) silicon microphones built in a 55 nm MOSFET technology is presented. The designed interface is made up by a pseudo-differential structure, based on two single-ended Super-Source-Followers with PMOS input device, to reduce Flicker noise contribution that would affect low frequency applications. The challenge of this design regards the implementation in 55 nm of high performance analog cells. The device performs output integrated noise in the [20 Hz 20 kHz] audio band of about-110 dBV(A), with a total power consumption of 270 µ W from a 1.5 V voltage supply. Acoustic Overload Point (AOP) reaches a mean value of 130 dBspl.

In automotive industry, every electronic device is driven by power switches. Indeed, the energy source is the car battery and it cannot, for instance, limit the output maximum voltage level. Consequently it could be higher than that supported by the load. The DC/DC Buck converter acts by limiting the output variables, according with the load specifications thereby ensuring its correct operation. The overall circuit will be composed of a power stage, the basic DC/DC converter, and a control loop, to provide a target output current value. This paper presents a control algorithm derived from an improved Peak Current Mode Control. The proposed algorithm defined Variable off-Time Peak Current Mode Control (VoT-PCMC) allows to contemporarily control in a DCDC converter the ripple and the average current values, leading to a reliable load driver. The algorithm operation is simulated and then tested on hardware using dSpace, a Rapid Control Prototyping set-up.

In this paper a 4th order low-pass continuous time analog filter in CMOS 28nm technology is presented. The filter complies with the specifications of the 60GHz next-generation transceivers. A novel circuital topology is presented suitable to perform the low-pass filtering of the in-band signal, while the in-band thermal noise is high-pass filtered, improving Signal-To-Noise-Ratio. 880MHz -3dB bandwidth is obtained by a prototype of the filter simulated in 28nm CMOS technology. The overall power consumption is 4.8mW from a single 1 V supply voltage. 51dB@THD>40dBc is the SNR at 0dB gain

The A-to-D converter here presented is part of a bigger system able to sense and monitor electrical/physical parameters in particles detectors, for LHC experiments. The CMOS integrated circuits operating in high-energy environments experience large leakage current and voltage/temperature variations. For this reason in LHC experiments, a proper sensing and monitoring system has been designed with the aim to provide real time information about the electrical/physical scenario for the detectors in LHC. The A-to-D converter has a resolution of 12 bits, is based on single slope architecture and is able to manage 32 input analog channels. The design is challenging for several reasons, considering the required conversion accuracy and the critical physical scenario. The entire A-to-D converter has been fully characterized with process-voltage-temperature variations, obtaining a definitive 11bit accuracy in the worst-case simulation corner. The A-to-D has been designed in CMOS 0.13 mu m technology, consumes 350 mu W (including dynamic power due to the digital circuits) and operates at 20MHz clock frequency, for a definitive 2.3kHz sample rate

This paper presents a design methodology for high-order class-D amplifiers, which covers the entire design flow, from specifications to component sizing. The methodology is validated with three design examples, namely a second-order, a third-order, and a fourth-order class-D amplifier. Moreover, the third-order class-D amplifier has been integrated on silicon and characterized, further confirming the validity of the whole design flow. The achieved results demonstrate that high-order class-D amplifiers can achieve Total-Harmonic-Distortion (THD) performance compatible with the specifications of high-end audio applications (THD approximate to 90 dB), which would be unfeasible with conventional first-order class-D amplifiers

A 90 nm-CMOS power-optimized analog baseband chain for ultra-low-power impulse-radio ultra-wideband (IR-UWB) receivers is presented. The proposed device merges the functions of a programmable gain amplifier (PGA) and a low-pass filter (LPF). It consists of the cascade of three biquadratic cells made up by opamps in a series-shunt configuration, which features high input impedance, low load effects in the cascade blocks, and better frequency response. The opamp parameters are included in the overall biquad transfer function. This allows getting very low power performance, since the opamp bandwidth is not required to be much larger than the filter cutoff frequency. Moreover, the current consumption is optimized according to the selected gain level (1.3 mA at 0 dB-gain up to 1.9 mA at 40 dB-gain). The PGA features a 0-40 dB programmable gain range with a 5 dB gain-step. The LPF performs a sixth-order 255 MHz low-pass frequency response. For the overall chain the IIP3 is 14 dBm at 0 dB gain, while the input referred noise is 12.5 nV/√Hz at 40 dB gain. © 2012 IEEE.

A 90nm, IR UWB, duty-cycled transceiver chipset, for operation from 7 to 9.8GHz and compliant to the IEEE802.15.4a and the upcoming IEEE802.15.6 standard, is presented. The complete, duty-cycled transmitter provides +1dBm peak output power, consuming 4.4mW. The receiver front-end shows +88dBm sensitivity at 0.85Mbps and a digital synchronization algorithm enables real-time duty cycling, resulting in a mean power consumption of 3mW. © 2011 IEEE.

High-speed low-resolution ADCs power consumption can be reduced with calibration that, however, presents some drawbacks like allocating a calibration time, calibration algorithm complexity, and calibration circuit implementation. In alternative, this paper presents a 1Gs/s 5-bit ADC without calibration, fabricated in a 90nm-CMOS. The device is based on the use of an improved version of double tail dynamic comparator that is designed to operate with a fixed bias current. This comparator presents a reduced kickback noise, allowing increasing the input transistors sizes. This improves matching and calibration is not needed. The resulting ADC performs 4.3b-ENOB up to Nyquist frequency at 1Gs/s, while consuming 7.65mW from a 1.2V supply. The ADC FoM of about 0.39pJ/conv that is at the state-of-the-art in this resolution&sampling frequency combination. © 2011 IEEE.

In this paper a 11MHz-f(@-3dB) continuous-time analog filter is presented. A low-noise circuital topology has been used based on typical Active-RC cells, like opamp-based integrators, and Active-G(m)-RC biquadratic cell. The basic idea is to synthesize two complex poles pairs (4(th)-Order Filter) using a single compact Active RC cell, which minimizes the in-band noise power contributions. A filter prototype, complying with WLAN baseband requirements, has been designed in CMOS 90nm technology. Thanks to noise power spectral density reduction - 48 mu V-rms output integrated noise (100kHz divided by 11MHz) at 0dB-pass-band gain - wide Dynamic Range (84dB@THD > 40dBc) is performed. In-band IIP3 is 10dBm, while the filter power consumption is 14mW

In this paper a low-cost integrated wide-range gas sensor interface based on a resistance-to-time converter is presented. The circuit in transistor level simulation achieves a linearity better than 0.5% over a range of 6 decades i. e. 1 k Omega divided by 1 G Omega, without requiring any calibration or auto-ranging. The maximum sensing time is 0.5 s, while measuring the highest resistance value. The state-of-the-art of this measurement has been improved by extending the acceptable input resistance range, while lowering the maximum power consumption. Moreover, a very high linearity has been achieved by canceling the parasitic effects of the multiplexer addressing the sensor matrix

This paper presents a digital amplitude modulator (DAM) for polar transmitter in 90 nm CMOS technology. It consists of 255 basic cells digitally activated by an 8-bit amplitude code to shape a non-constant envelope RF output. To reduce the aliases due to the discrete-time to continuous-time conversion a 2-fold interpolation has been implemented. It reaches an output power of -2.5 dBmRMS using a WLAN OFDM 64QAM modulation at 2.45GHz achieving -26.1 dB error vector magnitudes (EVM) and 18% drain efficiency. The 8-bit are segmented addressed. This results in a very compact 0.007 mm(2) chip area

This paper presents the design and implementation of a variable gain amplifier with an ultra low-power consumption of 56 mu W. This is achieved by using sub-threshold operation, 1V power supply and a minimum amount of current branches. After system-level optimization, a gain range of 47dB is implemented with 6dB per step programmability. The SNDR is better than 33dB for all gain settings, while the nominal signal bandwidth is 5MHz. The performance is measured on a test-chip in a 90nm CMOS technology

In this paper we present a complete low-voltage, low-power and high linearity CMOS interface circuit for fluxgate magnetic sensors for current measurement applications. The integrated circuit provides the correct excitation signal to the fluxgate sensors and reads-out the sensor signals from the sensing coils. The proposed circuit allows us to deal with sensors featuring different values of the excitation coil resistance and to process the sensing coil signals with a power consuption lower than 1 mW. The interface circuit consists of three different modules, namely a timing block, an excitation block and a read-out chain. The interface circuit, has been implemented with two different excitation circuits, operating at 5 V and 3.3 V, respectively, without any high-voltage process options. The read-out chain performs a synchronous demodulation of the even harmonics, in order to extract the value of the external magnetic field. Furthermore, it is possible to switch-on a 13 bit ADC, to provide at the output the demodulated signal as a digital word. ©2009 IEEE.

A low-power interface for readout and motion-control of a MEMS capacitive sensor is presented. The interface consists of a hybrid third-order sigma-delta modulator. The interface enhances the linearity and stability of the sensor by applying force feedback through bias voltage modulation. The modulator employs a hybrid, continuous + discrete -time topolooy, to reduce power consumption by avoiding a separate pre-amplifier for the sensor. Power consumption in the modulator is further reduced by an opamp sharing scheme. The interface is designed in 0.35um CMOS technology and is simulated in Cadence-Spectre. Simulation results are shown for a MEMS capacitive Microphone(1)

A CMOS interface for a piston-type MEMS capacitive microphone is presented. It performs a capacitance-to-voltage conversion by bootstrapping the sensor through a voltage pre-amplifier, feeding a third-order sigma-delta modulator. The bootstrapping performs active parasitic compensation, improving the readout sensitivity by -12dB. The total current consumption is 460uA at 1.8V-supply. The digital output achieves 80dBA-DR, with 63dBA peak-SNR, using 0.35um 2P/4M CMOS technology. The paper includes electrical and acoustic measurement results for the interface. © 2008 IEEE.

An integrated readout circuit for Lab-on-a-Chip applications is presented. The overall system consist of a 640x480 array of capacitor sensors and actuators. Sensors detect dielectric permittivity variation thanks to dielectrophoresis (DEP) process. Usually for this kind of applications an off-chip analog-to-digital converter is used. As a consequence, the noise floor increases and high signal-to-noise ratios are difficulty achieved. On the other hand, these applications requires a stringent noise floor specification (>10b) and a relaxed linearity (approximate to 8b). In this design, the noise coupled to the signal at the chip pad is reduced by using an on-chip analog-to-digital converter. The complete sensor readout channel is composed by two main blocks: a pre-amplifier with programmable gain and an algorithmic analog-to-digital converter with a 1.5-bit/stage architecture. Each one is realized with fully differential switched capacitor technique. In order to save chip area and power consumption a time sharing technique has been taken into account using a single operational amplifier for the pre-amplification stage and the conversion stage. The proposed A/D converter has 11b resolution, a sampling rate of about 100ksample/s and an input full-scale range of 1.2Vp-p differential. Simulation results show a SNR=65.7 dB and an ENOB value of 10.6b. Its power consumption is about 150 mu W. Readout chain is implemented in 0.35 mu m CMOS technology with a 3.3V supply voltage

An analog baseband chain for a multistandard (Bluetooth, WCDMA/UMTS, and WLAN) reconfigurable receiver in a 0.13 µm CMOS occupying 1.65 mm2 is presented. The circuit consists of an open-loop programmable-gain amplifier (PGA1), an Active-Gm-RC low-pass filter (LPF), and a closed-loop programmable-gain amplifier (PGA2). The chain gain can be programmed in the range -6dB-to-68 dB, while the input-referred noise (IRN) is 5 nV/sqry(Hz). A dynamic range (DR) larger than 82dB is achieved for a 1% total harmonic distortion (THD). The current consumption is minimized and adjusted for the different operation conditions, down to 11 mA for the full chain.

A low-power interface for readout and motion-control of a MEMS capacitive sensor is presented. The interface consists of a hybrid third-order sigma-delta modulator. The interface enhances the linearity and stability of the sensor by applying force feedback through bias voltage modulation. The modulator employs a hybrid, continuous + discrete -time topolooy, to reduce power consumption by avoiding a separate pre-amplifier for the sensor. Power consumption in the modulator is further reduced by an opamp sharing scheme. The interface is designed in 0.35um CMOS technology and is simulated in Cadence-Spectre. Simulation results are shown for a MEMS capacitive Microphone(1)

In this paper the design of a Programmable Gain Amplifier (0dB÷15dB, 3dB per step) embedded in the analog base-band chain for UWB Receivers in a standard 90nm CMOS technology is presented. The design has been realized using a proper Matlab procedure. Due to the large bandwidth required in the UWB Receivers, the procedure takes into account the second order effects related with the opamp parasitic capacitance and finite bandwidth. In this way the model guarantees to satisfy the IRN and transfer function accuracy requirements and to avoid linearity performance degradation. Thanks to the results obtained by the Matlab procedure, no capacitance are used in the PGA schematic. From a single 1.2V supply voltage, the PGA total current consumption is 3.5mA, the inband IIP3 is 15dBm and out-of-band IIP3 is 23dBm, the maximum IRN is 16nV/√Hz at 15dB gain. ©2008 IEEE.

This paper presents a complete gas-sensing system. The latter consists of a high-efficiency temperature control loop with a switching heater based on a custom digital control logic and of a wide-dynamic-range interface circuit able to operate without calibration. The temperature control loop is driven by a digital set-point and the simulations results show that it controls the temperature of the sensor over a range of 250 degrees C with an accuracy better than 0.5 degrees C. The temperature control logic is reconfigurable and can be used to control the temperature of sensors with different baseline resistance value and different sensitivity. The gas-sensing interface circuit is based on a resistance to frequency conversion and achieves, without calibration, a precision in resistance measurements of 0.5% over a range of 5 decades (dynamic range, DR=146 dB). All voltage references are reconfigurable and on chip buffered

This paper presents a low-power CMOS interface for a MEMS capacitive sensor. The interface has embedded force-balancing capability which improves the linearity of the readout for higher sound pressures. The interface also features a bias-charge control functionality to enhance the sensitivity of the microphone. The interface employs boot-strapped preamplifier for active parasitic capacitance compensation, followed by a 3rd-order sigma-delta modulator. The interface is designed in 0.35um CMOS technology and its brief simulation results in Cadence-Spectre are presented. © 2008 IEEE.

In this paper the design of the analog baseband chain for UWB Receivers in a standard 90nm CMOS technology is presented. The baseband chain is composed by the 5th order Elliptic analog low-pass filter and a Programmable Gain Amplifier (with up to 60dB gain). Due to the large UWB signal bandwidth (250MHz), the design has been carried-out using a MATLAB model taking into account the capacitance parasitics effect and the opamp finite bandwidth impact on the filter transfer function. From a single 1.2V supply voltage, the total power consumption is 13mA per channel, the in-band and out-of-band IIP3 is 20dBm and the maximum IRN for G>15dB is 9nV/√Hz. ©2008 IEEE.

In this paper an integrated readout circuit for Lab-on-a-Chip applications is described The system consist of a 320x320 array of capacitor sensors and actuators, the pitch of each site is 20 mu m. Sensors detect dielectric permittivity variation thanks to dielectrophoresis (DEP) process. Usually for this kind of applications the analog-to-digital conversion is carried out off chip but the major limitation in this case is the noise floor and then high signal to noise ratios are difficult to obtain. In fact, for these applications the noise floor specification (> 10b) is more critical than linearity (approximate to 8b). In order to reduce the amount of noise coupled to the signal at the chip pad and on the board, an on-chip analog-to-digital conversion is here implemented. The electronic interface is composed by two main blocks: a pre-amplifier with programmable gain and an algorithmic analog-to-digital converter with a 1.5-bit/stage architecture. Each one is realized by fully differential switched capacitor technique. The proposed AID converter has 11b resolution, a sampling rate of about 100ksample/s and an input full-scale range of IVp-p differential. Simulation results show a SNR=65.7 dB and an ENOB value of 10.6b. Readout chain is implemented in 0.35,mu m CMOS technology with a 33V supply voltage

A low-power impulse-radio ultra-wideband receiver is demonstrated for low data-rate applications. A topology selection study demonstrates that the quadrature analog correlation is a good receiver architecture choice when energy consumption must be minimized. The receiver operates in the 3.1–5 GHz band of the UWB FCC spectrum mask on channels of 500 MHz bandwidth. The pulse correlation operation is done in the analog domain in order to reduce the ADC sampling speed down to the pulse repetition rate, thereby reducing the power consumption. The receiver comprises a low-noise amplifier with full on-chip matching network, an RF local oscillator generation, two quadrature mixers, two analog baseband chains followed by two ADCs, and a clock generation network. The receiver is implemented in 0.18 mµ CMOS technology and achieves 16 mA power consumption at 20 Mpulses/s pulse repetition rate.

In this paper a 4th order low-pass continuous-time filter for a WLAN receiver is presented. The filter is designed to satisfy high-linearity performance while operating at very-low supply voltage. An improved bias circuit is used to operate with different opamp input and output common-mode voltages. The filter is realized in a standard 0.13um CMOS technology with V THN≈250mV and VTHP≈300mV. The filter is optimally operating with supply voltage as low as 550mV and slightly below. The filter architecture is composed by two Active Gm-RC biquadratic cells, which use a single opamp per-cell with a unity-gain-bandwidth comparable to the filter cut-off frequency. This reduces the total cell power consumption. The -3dB frequency is at 12MHz (for WLAN applications) and this is higher than any other low-voltage continuous-time filter. The -3dB frequency can be adjusted by means of a digitally-controlled capacitance array. The filter total area occupancy is 0.47mm2 and the total power consumption is 3.4 mW from a single 550mV supply. A 8dBm-in-band IIP3 and a 13.3dBm-out-of-band IIP3 demonstrate the validity of the proposal. © 2007 IEEE.

Radio transceivers relying on impulsed radio UWB signals show a strong potential for low data rate communications at an ultra low power consumption. They are for instance proposed by the IEEE 802.15.4a low-rate wireless personal area networks standard (LR-WPAN) to support low data rates, low power and low complexity short-range radio communications. In this paper, we give an overview of our recent UWB radio front-end designs along with new system simulation results, and derive specifications for a 15.4a receiver. The system simulations are used to balance the partitioning of gain, noise and distortion for next generation transceivers and allow to analyze the expected communication range of IEEE 802.15.4a systems in various channel conditions. The free-space wireless channel loss as well as 9 propagation scenarios are taken into account. © 2007 IEEE.

An opamp time-multiplexed topology of a third- order SigmaDelta modulator is presented in this paper. This topology implements a third-order noise transfer-function using only two opamps by sharing one opamp between second and the third integrators of the modulator. The simulated results are comparable to a low-power modulator with three separate opamps. The proposed SigmaDelta modulator is designed for a silicon microphone front-end. In the audio-band (20-20 kHz), it features a dynamic range above 80 dB, consuming 90 muWatts with a supply voltage of 1.8 V.

Continuous-time (CT) filters are widely used in signal processing but, owing to the large spread in the process parameters which determine their time constants, they require a tuning system to align their frequency characteristics. Several techniques have already been proposed in the literature and are commonly employed, but usually they require either a doubling of the filter circuitry or some complex self-calibration scheme, resulting in sensible area overhead or high computational complexity. Here, we present a novel tuning approach which can be applied to both master-slave and self-calibration arrangements and is based on the evaluation of a few samples of the input-output cross-correlation function of the filter, when the input signal is a finite length sequence of pseudorandom pulses. The key advantages of the proposed technique are basically the ease of generation of the input bit-stream and the simplicity of the circuitry required to sample the filter output and to perform the cross-correlation operation. As a consequence, the area overhead associated to the tuning circuitry is kept very small. Some simulation results of the application to the tuning of a low-Q telecommunication filter are given and an extension to the tuning of high-Q active filters is also explored in order to assess the effectiveness and robustness of the proposed technique.

A baseband filter synthesizer that takes a behavioural description of the design and produces an efficient transistor level implementation is presented. The tool optimizes the filter at the cascade level, providing the best trade-off between power consumption and dynamic range, and at the cell level, selecting minimum power solutions, through accurate analytical models and an efficient bi-quad topology. Differently from past cascade design techniques based on dynamic range optimization through linear programming [2], we focus on power minimization while guaranteeing minimum performance levels, given the increasing importance of power savings in hand-held devices. A synthesized filter has been realized in silicon demonstrating the effectiveness of our approach

A 10bit SAR-ADC implemented in a 1.2V 0.13 mu m CMOS with 1V(ppiff)-FS, based on capacitive-charge redistribution can be programmed with F-s up-to-6MS/s, guaranteeing an ENOB > 9b with a SFDR > 74dB. The static INL and DNL are 0.6LSB and 0.55LSB, respectively. On-chip reference buffer have been added and their power consumption dominates, giving a FoM approximate to 1pJ/conv. Sharing these buffers with other blocks in SoC structure, reduces the ADC power consumption to 200 mu W and the FoM approximate to 0.1pJ/conv. This appears an attractive solution for embedded ADC

In this paper an integrated CMOS front-end circuit for a micro-integrated Fluxgate magnetometer is proposed. The system is based on excitation block, that feeds the excitation coil of the sensor and a read-out block that sense the voltage of the pick-up coils. To sense the output signal, the second harmonic detection principle has been chosen to achieve a good compromise between power consumption and noise requirements. An integrated low pass Sallen-Key filter has been used to extract the dc signal after the demodulation. The preliminary measurements, performed with a PCB sensor, show a sensitivity of 920 V/T and a linearity error of 6% full scale. The circuit has been realized in a standard 0.35 um CMOS process. The power consumption is 8 mW @ 3.3V for the excitation and read-out parts and unit and 42 mW @ 5V for the output power stage. © 2006 IEEE.

A Switched Capacitor (SC) interface for a capacitive MEMS microphone is described in this paper. By properly switching the sensor, parasitic insensitive ac-coupling readout is directly performed without the need of a large bias resistor. The SC readout-circuit offers the advantages of a differential- topology for a single-ended sensor without accurate capacitor matching techniques. © 2006 IEEE.

This paper presents a novel 10-bit pipeline A/D converter for low noise, self-triggered applications. The proposed A/D converter does not require any timing signal (clock) in order to carry out the conversion, assuming that a sampled signal is provided at the input. The circuit basically operates as "combinatorial logic", propagating the partial conversions and the residues through the various stages asynchronously. The presented ADC has been designed in a standard 0.35um CMOS technology and the conversion period is lower than 500ns (i.e. 2MHz data rate). The power consumption is 39mW from a 3.3 V power supply. The total chip area without pads is 2.24 mm2.

In this paper a novel 10-bit pipeline A/D converter for low noise, self-triggered sensors is presented. The main innovative feature of the proposed A/D structure is the concept that a pipeline ADC may behave as a combinatorial logic and may operate without any timing signal (clock) in order to produce the conversion (assuming that a sampled signal is provided at the input). This concept is validated by the experimental results here reported. A prototype ADC has been fabricated in a standard 0.35 mu m CMOS technology, has an active area of 2.24mm(2), provides a conversion in 2.5 mu s (400kS/s) and consumes 14mW from a 2.3V power supply

The wireless networks popularity rapidly requires a significant effort on low-power, low-cost, and highly integrated RF ICs, where the power consumption reduction of the transceiver and of each block becomes of fumdamental importance. Analog base-band continuous-time filters embedded in the receiver path are here addressed with three examples. The first example is an Active-Gm-RC filter which uses the opamp frequency response to synthesize the filter behaviour. The second example is a source-follower-based filter cell. A large linearity is achieved for a low over-drive. This with the possibility of realizing a full biquadratic cell in a single branch, requires a low power consumption. Both these examples are suited for UMTS & WLAN receivers. The last example is the gm-gm-C approach which features low-power wide-band CMOS continuous-time low-pass filters with medium resolution, as it is the case of a UWB base-band filter. © 2006 IEEE.

In this paper we present the design and testing of an integrated wide-range interface for resistive sensors. The ASIC consists of a multi-scale trans-resistance continuous time amplifier (programmed by selecting a feedback resistor from an array), followed by a 13-bit incremental A/D converter. After calibration, employed to cancel offset and gain error mismatch between scales, the device shows a worst case error in the resistance value measurement of about 0.1% over a range of more than 5 decades [100 Omega-20M Omega]

A complete front-end system for resistive gas sensor array is presented. The system is composed by a substrate temperature control circuit and by a read-out circuit. The temperature control allows maintaining a 100 degrees C temperature gradient selected in the temperature range [150 degrees C-350 degrees C] on the array of sensor. The gas sensor read-out circuit, which acts like a resistance-to-period converter, is suitable to be interfaced to a microcontroller in order to achieve a resolution error lower than 0.5% for a resistance ranging in [300k Omega-300M Omega]. The full device, including 8 read-out channels and 2 temperature control systems, is designed in a standard 0.35 mu m CMOS technology. The die area is 1.8mm(2) with a total power consumption of 30mW from a single 3.3V supply voltage