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This thesis investigates the use of massively parallel fine-grained processor arrays to increase computational performance. As processors move towards multi-core processing, more energy-efficient processors can be designed by increasing the number of processor cores on a single chip rather than increasing the clock frequency of a single processor. This can be done by making processor cores less complex, but increasing the number of processor cores on a chip. Using this philosophy, a processor core can be reduced in complexity, area, and speed to form a very small processor which can still perform basic arithmetic operations. Due to the small area occupation this can be multiplied and scaled to form a large scale parallel processor array to offer a significant performance. Following this design methodology, two fine-grained parallel processor arrays are designed which aim to achieve a small area occupation with each individual processor so that a larger array can be implemented over a given area. To demonstrate scalability and performance, SIMD parallel processor array is designed for implementation on an FPGA where each processor can be implemented using four ‘slices’ of a Xilinx FPGA. With such small area utilization, a large fine-grained processor can be implemented on these FPGAs. A 32 × 32 processor array is implemented and fast processing demonstrated using image processing tasks. An event-driven MIMD parallel processor array is also designed which occupies a small amount of area and can be scaled up to form much larger arrays. The event-driven approach allows the processor to enter an idle mode when no events are occurring local to the processor, reducing power consumption. The processor can switch to operational mode when events are detected. The processor core is designed with a multi-bit data path and ALU and contains its own instruction memory making the array a multi-core processor array. With area occupation of primary concern, the processor is relatively simple and connects with its four nearest direct neighbours. A small 8 × 8 prototype chip is implemented in a 65 nm CMOS technology process which can operate at a clock frequency of 80 MHz and offer a peak performance of 5.12 GOPS which can be scaled up to larger arrays. An application of the event-driven processor array is demonstrated using a simulation model of the processor. An event-driven algorithm is demonstrated to perform distributed control of distributed manipulator simulator by separating objects based on their physical properties.

JPEG encoding is a powerful image compression algorithm capable of compressingimage data at the cost of image quality. A variety of architectures implement JPEG encoding, each leveraging either serial execution superiority (general-purpose programmable processors), massive parallelization abilities (GPUs), or dynamic architecture arrangements (FPGAs). However, all these architectures need help to simultaneously handle the serial and parallel components of the JPEG encoding algorithm. This thesis proposes 29 JPEG encoder implementations on the KiloCore platform (a fine-grain manycore processor array), compares each algorithm to one another, and compares the top algorithms to designs on differing architectures. This work benchmarks throughput, throughput per area, energy per megapixel encoded, and energy-delay product across 29 KiloCore JPEG encoder versions. Furthermore, this work compares the top KiloCore designs against JPEG implementations on a Xilinx Zynq-7000 FPGA (VISENGI), TI C66x Embedded Processor, Intel i9 9900 CPU (libjpeg-turbo), and Intel Platinum 8168 with an Nvidia A100 GPU (nvJPEG). JPEG encoding implementations on KiloCore require low amounts of energy while still reaching competitive throughput. JPEG encoding implementations on KiloCore achieve higher throughput than the C66x and Intel i9 9900 JPEG encoders by at least 6.6×. JPEG encoding implementations on KiloCore have the lowest area usage and have the highest throughput per area by 1.45× to 100×. JPEG encoding implementations on KiloCore have the lowest energy per megapixel encoded of tested general-purpose processors, by 1.88× to 100×. Finally, JPEG encoding implementations on KiloCore boast a 20× to 261,733× lower energy-delay product than its general-purpose industry competition.