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The revolution in electronics enabled by Moore’s Law has been driven historically by the ability to fabricate ever smaller features lithographically on planar semiconductor platforms. In recent years, this has been slowing down due to the myriad of problems in short channel CMOS technologies. Research is now focusing on realizing Moore’s law by architectural innovation, involving novel circuits and computation paradigms. There has been intense interest and activity directed towards designing logic circuits with memory elements. This is mainly driven by ideas like in-memory compute where logic operations are performed at the memory location in order to overcome the memory-wall bottleneck. Resistive-switching random-access memory (RRAM)/ memristors has a great potential to be the future of non-volatile memory owing to its CMOS compatibility, read-write endurance, power and speed. We describe novel high speed logic circuits for adders and multipliers built with RRAM to support the concept of logic-in-memory. These circuits have significant speed/area/power improvements over the existing designs. The complexity involved in computation in terms of controlling the basic gates, sequence of operations etc. has been significantly reduced. RRAM properties are exploited with the help of a well-known analog element called current mirror. Previously known logic-implication technique to realize digital gates comes with a serious limitation of limited fan-out. By using current mirrors, this limitation can be overcome, enabling more logic operations to run in parallel. Results show that the delay for even an XOR operation can be reduced to 1 cycle, compared to the 5 cycles taken by logic implication. Spice simulations are done with known RRAM models. Simulation results show significant improvement in power consumed over the existing designs. The design of different adders and multipliers are also described. Metrics like area, power and latency are compared, and it shows significant improvement over the state-of-the-art.

Successful exfoliation of graphene and discoveries of its unique electrical and thermal properties have motivated searches for other quasi two-dimensional (2D) materials with interesting properties. The layered van der Waals materials can be cleaved mechanically or exfoliated chemically by breaking the relatively weak bonding between the layers. In this dissertation research I addressed a special group of inorganic van der Waals materials - layered transition metal dichalcogenides (MX2, where M=Mo, W, Nb, Ta or Ti and X=S, Se or Te). The focus of the investigation was electronic properties of thin films of TaSe2 and MoS2 and their device applications. In the first part of the dissertation, I describe the fabrication and performance of all-metallic three-terminal devices with the TaSe2 thin-film conducting channel. The layers of 2H-TaSe2 were exfoliated mechanically from single crystals grown by the chemical vapor transport method. It was established that devices with nanometer-scale thickness channels exhibited strongly non-linear current-voltage characteristics, unusual optical response, and electrical gating at room temperature. It was found that the drain-source current in thin-film 2H-TaSe2-Ti/Au devices reproducibly shows an abrupt transition from a highly resistive to a conductive state, with the threshold tunable via the gate voltage. Such current-voltage characteristics can be used, in principle, for implementing radiation-hard all-metallic logic circuits. In the second part of the dissertation, I describe the fabrication, electrical testing and measurements of the low-frequency 1/f noise in three-terminal devices with the MoS2 thin-film channel (f is the frequency). Analysis of the experimental data allowed us to distinguish channel and contact noise contributions for both as fabricated and aged devices. The noise characteristics of MoS2-Ti/Au devices are in agreement with the McWhorter model description. The latter is contrary to what is observed in graphene devices, where the noise spectral density does not follow the carrier number fluctuation model. The trap density extracted from the noise measurements is on the order of 1.5x1019 eV-1cm-3 and 2x1020 eV-1cm-3 for as fabricated and aged samples, respectively. These values are of the same order of magnitude as those in high-k MOSFETS. These results of this dissertation research may lead to new applications of van der Waals materials.

Computation underlies the organization of cells into higher-order structures; for example, during development or the spatial association of bacteria in a biofilm. Each cell performs a simple computational operation, but when combined with cell-cell communication, intricate patterns emerge. Here, we study this process by combining a simple genetic circuit with quorum sensing in order to produce more complex computations in space. A simple NOR gate is constructed by arranging two tandem promoters that function as inputs to drive the transcription of a repressor. The repressor inactivates a promoter that serves as the output. Individual colonies of E. coli carry the same NOR gate, but the inputs and outputs are wired to different orthogonal quorum sensing "sender" and "receiver" devices. The quorum molecules form the wires between gates. By arranging the colonies in different spatial configurations, all possible 2-input gates are produced, including the difficult XOR and EQUALS functions. The response is strong and robust, with 5- to >300-fold changes between the ON and OFF states. This work helps elucidate the design rules by which simple logic can be harnessed to produce diverse and complex calculations by rewiring communication between cells.

The development of controllers for autonomous intelligent agents given a simple task is relatively straightforward and basic techniques can be used to develop such controllers. However, as agents are given more than one task, using basic techniques for developing effective controllers quickly becomes impractical. State and action abstraction are frequently used to counter this explosion of complexity and to make the development of effective controllers for complex problems practical. Unfortunately, most of the work in the literature has focused on complex tasks comprised of sequences of simpler tasks and the more complex tasks comprised of many concurrent, interfering, and non-episodic (CINE) tasks have received little attention. As a result, this dissertation seeks to address this deficiency by providing the first known empirical investigation into the effects of each of these types of abstraction on CINE tasks. The results of this investigation demonstrate that for the single-agent and multi-agent problem domains used, abstraction of the controller's actions provides more benefits in the development and performance of effective controllers than abstraction of the agent's state.

Device physics limitations of conventional complementary metal-oxide semiconductor (CMOS) transistors are likely to cause diminishing integrated circuit performance improvement in the sub 100-nm regime. At these dimensions, quantum effects become prominent leading to realization of devices utilizing quantum-mechanical tunneling transport mechanisms for obtaining picosecond device switching speeds. The negative differential-resistance (NDR) current-voltage (I-V) characteristic of such devices, achieved due to resonant tunneling, is also ideally suited for the design of compact self-latching logic circuits. While resonant tunneling devices have been demonstrated using III-V materials, their large absolute current values and low integration levels have limited their use to niche high-performance small-scale circuits. Given the advantages of resonant tunneling devices, it is attractive to envision compact, high-functionality NDR circuits implemented in a technology such as CMOS that offers low power dissipation and very high integration levels. Even as research in cointegration of resonant tunneling devices in Silicon, referred to as quantum MOS (QMOS), is ongoing, this dissertation presents novel combinational and bistable logic families, and compact flip-flop circuits using resonant tunneling diodes (RTDs) and MOS transistors. Analytical studies of static and dynamic QMOS performance parameters yield expressions for theoretical circuit comparison with CMOS, and also for optimizing RTD characteristics. QMOS circuits are characterized using SPICE simulation, and simulation-based comparison of QMOS and CMOS circuits highlights potential area-power-delay savings of this new circuit technique. The folded I-V characteristic of RTDs allows gate-level bistable-clocked-mode system operation. Performance improvement of such fine-grained QMOS pipelines arises from compactness of logic design, elimination of pipeline latch area, delay and power overhead, and high switching speed of the RTD. A pipelined carry-save multiplier and a 32-bit parallel correlator are designed to study the system-level advantages of QMOS logic. In particular, signal processing systems and communication systems benefit from fine-grained pipelining due to minimal data dependence and large volume of similar computations at each cycle. In the absence of a fabrication process that cointegrates RTDs in Silicon, a study of various QMOS prototyping schemes is presented that identifies the best means to verify system-level behavior of QMOS circuits while research in RTD-CMOS cointegration continues.

A software interface between a firmware documentation system and a logic simulator named TEGAS-51 is described. The interface accepts PALASM2 inputs for PAL files. The output is an ASCII file which defines the firmware parts in TEGAS-5 format. Modules are written in FORTRAN and command routines are written in DCL on VAX 11/780 machines. No system calls are required, so portability is maintained. Limitations include the inability to load two different programs in identical firmware parts on the same design, but this can be overcome. 1GE/Calma Corporation trademark 2MMI Corporation trademark

A program has been written for the Texas Instrument's TI-59 hand-held calculator implementing the Quine-McCluskey minimization method for logic circuit design. This program is contained on multiple magnetic cards and provides the user with the capability for combinational logic minimization of circuit design problems containing up to six variables.