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This thesis is a comparative analysis of the representation of foreigners in Ancient Greece and China. It argues that Archaic and Classical Greece was an integral part of the wider Eastern Mediterranean and Near Eastern civilization and that this had a major impact on the ways in which the Greeks chose to represent foreigners in their literature. It also seeks to show that the Ancient Chinese of the Han dynasty were as assertive as the Greeks in claiming their ethnic superiority over non-Chinese, but concludes that, although the two cultures shared the same breadth and variety of prejudices towards outsiders, they, nonetheless, due to historical, political and cultural circumstances, chose to emphasize different categories of differentiation. Through the examination of the two principal texts chosen for the analysis, the Shiji and the Histories, and other primary sources, the thesis demonstrates the similarities and differences between the Greek and Han Chinese representations of foreigners, both nomadic and sedentary. It is observed that both the Chinese and the Greek representations of nomads are remarkably similar, reflecting the real, noticeable differences in material culture between the sedentary worlds of the Eastern Mediterranean and the Zhong Yuan (central China) on the one hand and the arid steppe world on the other. However, in contrast, it is observed that the Chinese and the Greeks differ markedly in their approach and attitudes towards their sedentary neighbours. It is noted that the most significant differentiating features identified by Chinese writers between the Zhong Guo (China) and the barbarian are always material culture and moral standards of behaviour, relating mainly to ritual practice. This, it is argued in the thesis, is a reflection of the cultural dominance ofthe Han empire in the East Asian region that saw no significant rivals emerge to challenge that ideologically sinocentric world order. In contrast, the Greeks, who were relative new-comers to the family of civilized ethne in the Eastern Mediterranean and the Near East and who were acutely conscious of the youth of their civilization vis-a.-vis the much older cultures of the Near East, chose to emphasize more subjective categories of differentiation to highlight their ethnic specificity and 'superiority' over their sedentary rivals.

Developing strong and lightweight polymer composites is a high priority in industry. Carbon black and glass fibers are typically incorporated as fillers to enhance the mechanical properties of polymer composites. However, these fillers have limitations in controlling the composition, dispersing adequately within the polymer matrix, and achieving high transparency. To overcome the limitations of the currently available fillers, polymerization-induced self-assembly (PISA) derived nanofibers (worms) are being considered as an alternative. In this thesis, PISA-derived worms were synthesized via reversible addition-fragmentation chain transfer (RAFT) aqueous emulsion polymerization and applied as reinforcement filler in poly(styrene-stat-n-butyl acrylate) polymer nanocomposites. The influence of initial droplet size on nucleation mechanisms in aqueous heterogeneous polymerization of styrene was first investigated using hydrophilic poly(acrylic acid-stat-poly(ethylene glycol) methyl ether acrylate) P(AA-stat-PEGA) macroRAFT agent. As the initial droplet size increases, the loci of polymerization changes from monomer droplets (miniemulsion polymerization) to self-assembled block copolymer micelles (RAFT aqueous emulsion PISA). These results provide a mechanistic understanding of the nucleation mechanisms and their influence on nanoparticle morphology. Secondly, worms comprising P(AA-stat-PEGA) as a corona block were synthesized via RAFT aqueous emulsion PISA. The theoretical glass transition temperature (Tg) of the worms was varied from −53 to 100 °C by adjusting the styrene (St): n-butyl acrylate (nBA) molar ratios. The synthesized P(St-stat-nBA) core worms (Tg ≈ 27.1 °C) were successfully employed as reinforcement filler in P(St-stat-nBA) polymer nanocomposites. The mechanical properties of the polymer nanocomposites depended strongly on worm loading and presence of crosslinking in the core-forming block. A large enhancement in toughness was achieved with 1 wt% crosslinked worm. Lastly, film formation of PnBA core spheres and worms was investigated. Worm film exhibited higher tensile strength and strain at break than sphere film, demonstrating that the mechanical properties of films can be tuned depending on the nanoparticle morphology. In summary, the synthesized PISA-derived P(AA-stat-PEGA)-b-P(St-stat-nBA) worms were successfully employed as fillers. This thesis provides new insights into the synthesis of alternative fillers with tunable Tg and the application of worms in polymer nanocomposites and films.

General-purpose graphics processing unit (GPGPU) is one of the most popular many-core acceleratorsthat deliver a massive computing power in parallel applications. GPGPUs mainlyrely on the hardware multithreading to hide a short pipeline stall and a long memory latency.Thus, the performance of GPGPU can be signicantly aected by how GPGPU'shardware multithreading is applied. However, nding the optimal hardware multithreadingis a complex problem since there are many aspects to be considered. This work studies themechanisms for improving the eectiveness of hardware multithreading. First, it studiesthe various scheduling policies and proposes an adaptive scheduling policy that chooses thebest scheduling policy at runtime. In addition, it proposes simple but eective warp throttlingmechanism that can increase the cache locality. Furthermore, it proposes a hardwareprefetching mechanism to extend the memory latency hiding degree of hardware multithreading.Finally, it shows how a limited scalability of the conventional cache miss handling architectureconstrains the degree of hardware multithreading and proposes the highly scalablecache miss handling architecture.

With the scaling of technology nodes, the speed performance of microprocessors has rapidly improved but the scaling of off-chip input/output (I/O) bandwidth is limited by physical pin resources and interconnect technologies. In order to reduce the performance gaps, new interface techniques have emerged and the marketplace has moved towards higher levels of integration with system on a chip (SoC) implementations. The advent of new techniques, however, has led to new challenges on the semiconductor and automated test equipment (ATE) industries. The relatively slow growing ATE technology comparing to I/O speeds especially intensifies manufacturing test issues. Testing high speed I/O timing parameters requires expensive high performance test equipment with high accuracy and resolution. The requirements increase integrated circuit (IC) manufacturing costs and thus test issues have become critical. This thesis focuses on on-chip test methods to improve test accuracy and reduce test costs for high speed double data rate (DDR) memory I/Os using source synchronous clocking. For testing the I/O timing parameters, a phase interpolator based on-chip timing sampler using a cycle-by-cycle control method was developed. This circuit generates data and clock patterns and controls the time delay between data and clock to detect the timing mismatch which indicates timing degradations. The on-chip timing sampler was implemented as a built-in self test (BIST) circuit for low-cost parametric timing measurements. The BIST scheme was fabricated with a 0.18-um CMOS process technology. Using the static and dynamic modes, measurement results are obtained for the I/O timing parameters such as the setup and hold times, input voltage-level variations tolerances, duty distortion tolerances and data skews. Moreover, a delay mismatch measurement method was developed to improve measurement accuracy using a simple control circuit. This delay mismatch detector measures timing mismatches between data and clock paths and then the timing mismatches are converted to timing specifications. This scheme is also implemented along with analog to digital converter (ADC) to collect digital test results supporting low-cost system-level tests. Thus, the low-frequency test results show that our on-chip measurement techniques provide an attractive low-cost solution and is effectively applied for testing high speed source synchronous systems.