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In this thesis the charge dynamics in novel colloidal quantum dots (QDs) are investigated using ultrafast transient absorption spectroscopy, and other complementary spectroscopic techniques, to examine the mechanisms and rates of charge carrier relaxation on sub-nanosecond timescales. A deeper understanding of specific charge relaxation processes in various QD systems is achieved, with implications for the optimisation and understanding of quantum dot applications, particularly for the enhancement of QD sensitised photovoltaics. Surface mediated charge trapping is a process which reduces the efficiency of QD based devices and complicates the analysis of QD charge dynamics. We compare the dynamics in CdTe QDs before and after surface treatment with chloride ions which we show to be capable of completely eliminating trapping, evidenced by attaining near unity photoluminescence quantum yields. This unique comparison enabled isolation of the effects of traps which has not been achieved by any other studies. Both hot and cold electron trapping processes are identified, which if unrecognised in other QD studies could lead to significant misinterpretation of results. Charge transfer in quinone conjugated CdTe/CdS QDs is investigated for a range of average acceptor to quantum dot ratios. The charge transfer process competes with radiative recombination, resulting in efficient quenching of the PL intensity with promising applications in bio-sensors. A complex behaviour in the charge dynamics is discovered which suggests a relationship between charge transfer and surface mediated charge trapping. We report the first measurement of multiple exciton generation (MEG) in quasi-Type II core/shell InP/CdS QDs. The quantum yield of MEG is found to be 1.22 ± 0.01 for an excitation photon energy equivalent to three times the band gap. This is comparable to Type I InP core/shell QDs, but the quasi-Type II structure brings several effects which have the potential to enhance device performance. The enhancement to solar cell efficiency expected from such effects are demonstrated using the Detailed Balance model.

Replacing the traditional SiO2 gate oxide in a MOSFET with ferroelectric HfO2 creates a 1T memory device referred to as a FeFET. The bi-stable polarization states cause a retained threshold voltage shift known as the memory window. Ferroelectric HfO2 offers a number of material and electrical advantages over perovskite based ferroelectrics such as PZT or SBT. Due to its use as a high-k dielectric, the ALD capability and etch characteristics of hafnium oxide are well documented. Ferroelectric HfO2 has been shown to be thermally stable up to 1000 C, making gate first FeFET processes feasible. Electrically, HfO2 is capable of achieving much larger memory windows due to a high coercive field, on the order of 1-2 MV/cm. This property also allows for much thinner films (nm) without degradation of the memory window, and the potential for finFET applications. This work focuses on the integration of aluminum doped HfO2 into a standard RIT FET process. Previous work at RIT has led to the development of an ALD recipe and subsequent anneal to induce the ferroelectric crystal phase in Al:HfO2. In this work, n-channel MOSFETs with aluminum gate/20nm Al:HfO2/p-Si have been de- signed and fabricated. Etching of Al:HfO2 has been investigated using chlorine based plasma etching. The devices show a subthreshold slope of 75 mV/dec. Pulse testing reveals significant threshold voltage shift due to electron charge trapping commonly observed in Hf based dielectrics. I-V characteristics show mobility degradation, which is caused by Coulomb scattering as a result of trapped charges. For the devices to exhibit ferroelectric behavior with high on-state current, measurement and mitigation of charge trapping need to be further investigated.

While need for embedded non-volatile memory (eNVM) in modern computing systems continues to grow rapidly, the options have been limited due to integration and scaling challenges as well as operational voltage incompatibilities. Introduced in this work is a unique multi-time programmable memory (MTPM) solution for advanced high-k/metal-gate (HKMG) CMOS technologies which turns as-fabricated standard logic transistors into eNVM elements, without the need for any process adders or additional masks. These logic transistors, when employed as eNVM elements, are dubbed “Charge Trap Transistors” (CTTs). The fundamental device physics, principles of operation, and technological breakthroughs required for employing logic transistors as eNVM are presented. Implementation of CTT eNVM in 32 nm, 22 nm, 14 nm, and 7 nm production technologies has been realized and demonstrated in this work. The emerging memory technology landscape and the space that the CTT technology occupies therein are examined.The motivation behind this work is to develop an eNVM technology that is completely process/mask-free, multi-time programmable, operable at low/logic-compatible voltages, scalable, and secure. The CTT technology satisfies all of the aforementioned criteria. CTTs offer a data retention lifetime of > 10 years at 125 �C and an operation temperature range of -55�-125� C. Hardware results demonstrate an endurance of > 10^4 program/erase cycles which is more than adequate for most embedded applications. Hardware security enhancement, on-chip reconfigurable encryption, firmware, BIOS, chip ID, redundancy, repair at wafer and module test and in the field, performance tailoring, and chip configuration are a few of the applications of CTT eNVM. Moreover, the CTT array in its native (unprogrammed) state measures very well as an entropy source for potential PUF (Physically Unclonable Function) applications such as identification, authentication, anti-counterfeiting, secure boot, and cryptographic IP. In addition to the numerous digital applications, CTTs can also be utilized as an analog memory for applications like neuromorphic computing for machine learning (ML) and artificial intelligence (AI).

Organic semiconductors could have wide-ranging applications in lightweight, efficient electronic circuits. However, several fundamental questions regarding organic electronic device behavior have not yet been fully addressed, including the nature of chemical charge traps, and robust models for injection and transport. Many studies focus on engineering devices through bulk transport measurements, but it is not always possible to infer the microscopic behavior leading to the observed measurements. In this thesis, we present scanning-probe microscope studies of organic semiconductor devices in an effort to connect local properties with local device behavior. First, we study the chemistry of charge trapping in pentacene transistors. Working devices are doped with known pentacene impurities and the extent of charge trap formation is mapped across the transistor channel. Trap-clearing spectroscopy is employed to measure an excitation of the pentacene charge trap species, enabling identification of the degradationrelated chemical trap in pentacene. Second, we examine transport and trapping in peryelene diimide (PDI) transistors. Local mobilities are extracted from surface potential profiles across a transistor channel, and charge injection kinetics are found to be highly sensitive to electrode cleanliness. Trap-clearing spectra generally resemble PDI absorption spectra, but one derivative yields evidence indicating variation in trap-clearing mechanisms for different surface chemistries. Trap formation rates are measured and found to be independent of surface chemistry, contradicting a proposed silanol trapping mechanism. Finally, we develop a variation of scanning Kelvin probe microscopy that enables measurement of electric fields through a position modulation. This method avoids taking a numeric derivative of potential, which can introduce high-frequency noise into the electric field signal. Preliminary data is presented, and the theoretical basis for electric field noise in both methods is examined.

Negative Bias Temperature Instability (NBTI) in silicon based metal-oxide-semiconductor-field-effect-transistors (MOSFETs) has been recognized as a critical reliability issue for advanced space qualified electronics. The phenomenon manifests itself as a modification of threshold voltage (Vth) resulting in degraded signal timing paths, and ultimately circuit failure. Despite the obvious importance of the issue, a standard measurement protocol has yet to be determined. This is a consequence of a large amount of complexity introduced by the strong dependencies of NBTI on temperature, electric field, frequency, duty cycle, and gate dielectric composition. We have improved upon the traditional measurement techniques which suffered from an underestimation of the magnitude of Vth shifts because they failed to account for trapped charge relaxation. Specifically, we have developed a means for measuring the maximum effect of NBTI by virtue of a method that can continuously monitor the Vth(t) without having to remove the stressing voltage. The interpretation methodology for this technique is explained in detail and the relevant approximations are justified. We have evidenced temperature and vertical electric field dependent Vth shifts in SiO2 and HfSiON devices. Furthermore, we have collected substantial evidence that the traditional \uf044Vth=At\uf061 analysis fails to explain the experimental data in the early time domain. Finally, we have discovered that \uf044Vth(t) on p-channel field effect transistors with HfSiON gate dielectrics is dependent upon the magnitude of Vds during the stressing cycle. To our knowledge this is not anticipated by any prior modeling attempts. We justify the exclusion of short channel effects as a possibility, leading us to conclude that positive charge in the dielectric stack is laterally

Nanoscale p-channel transistors under negative gate bias at an elevated temperature show threshold voltage degradation after a short period of stress time. In addition, nanoscale (45 nm) n-channel transistors using high-k (HfO2) dielectrics to reduce gate leakage power for advanced microprocessors exhibit fast transient charge trapping effect leading to threshold voltage instability and mobility reduction. A simulation methodology to quantify the circuit level degradation subjected to negative bias temperature instability (NBTI) and fast transient charge trapping effect has been developed in this thesis work. Different current mirror and two-stage operation amplifier structures are studied to evaluate the impact of NBTI on CMOS analog circuit performances for nanoscale applications. Fundamental digital circuit such as an eleven-stage ring oscillator has also been evaluated to examine the fast transient charge transient effect of HfO2 high-k transistors on the propagation delay of ring oscillator performance. The preliminary results show that the negative bias temperature instability reduces the bandwidth of CMOS operating amplifiers, but increases the amplifier's voltage gain at mid-frequency range. The transient charge trapping effect increases the propagation delay of ring oscillator. The evaluation methodology developed in this thesis could be extended to study other CMOS device and circuit reliability issues subjected to electrical and temperature stresses.

Recent advancements in gate stack engineering has led to the development of aggressively scaled, high mobility, high-k dielectric based NMOSFETs with metal gates. Most of the current literature on the subject also stressed on the need for a high temperature process step to attain the high mobility under minimal change of effective oxide thickness. However, the physical origin of high mobility is not well understood. In this work, fundamental insight into the necessity of the high temperature process step is provided. Novel experimental strategies are developed to understand the impact of interface states and bulk traps separately and exclusively on channel mobility. It is conjectured that the interface states at the SiO2⁄(100) bulk-Si interface are identical in nature (as far as coupling with the channel electrons is concerned) to those at the high-k⁄SiO2⁄(100) bulk-Si interface. Thus, the response of interface states on channel electrons in high-k insulator based NMOSFETs is properly calibrated by a novel thermal desorption of hydrogen experiment on SiO2⁄(100) bulk-Si NMOSFETs to yield a highly accurate parameterized equation. The value of interface state response parameter determined by the aforementioned experiment is compared with theoretical predictions, and independently determined projections from electrical stress measurements. The impact of transient charging on transport in the channel is investigated. It is conclusively shown that remote charge has minimal impact on mobility in the channel. The role of nitrogen induced fixed oxide charge is studied on a set of Hf-silicate samples. Role of soft optical phonon scattering and the beneficial impact of metal gates on soft optical phonon limited mobility are thoroughly investigated both theoretically and experimentally. Conclusions are drawn on the fundamental limit of mobility attainable in high-k dielectric based NMOSFETs.

Scaling of advanced CMOS device dimensions, as set forth for future technology nodes by the International Technology Roadmap for Semiconductors (ITRS), will require reduction of the equivalent oxide thickness (EOT) of gate dielectrics below a point that can be physically realized using silicon dioxide. In order to continue EOT scaling below ~1.5 nm and reduce gate leakage current, higher dielectric constant materials will be needed to replace SiO2. Hafnium-based dielectrics are being widely investigated as potential candidates for the gate dielectric application. Their charge trapping characteristics were identified as a primary issue preventing the introduction of Hf-based materials into CMOS technology, potentially causing threshold voltage instability and mobility degradation. Several measurement techniques can be used to study and quantify charge trapping: Capacitance-Voltage (C-V) hysteresis, alternating stress and sense Vfb/Vt instability, charge pumping, and fast transient Id-Vg measurement. While each of these techniques can provide information on specific aspects of the charge trapping phenomenon, some measurements are more convenient (e.g., less time consuming), and some may be more sensitive for resolving subtle differences between the experimental samples. In particular, C-V hysteresis measurements can be used to monitor Vfb shifts for evaluation of hysteresis. A more quantifiable technique that uses a constant voltage gate dielectric stress (CVS) with interspersed limited-voltage-range C-V measurements around flatband can be used. Although systematic, this technique results in the de-trapping of some of the charge between the stress and sense sequence. A more useful approach is the charge pumping (CP) technique. Fixed-amplitude charge pumping (FA CP) measures interface state densities, whereas variable-amplitude (VA CP) measures trap densities in the high-k bulk. However, interpretation of the data can be complicated due to the gate and source/drain leakage. Another powerful technique is the fast transient Id-Vg measurement in the microsecond regime. The shift of the Id-Vg curves generated by the up and down swing of a trapezoid pulse (i.e., Delta Vt) corresponds to the amount of the trapped charge. Our data indicates that the fast transient and charge pumping results on the charge trapping correlate rather well (though there are differences in values) while the 'stress and sense' approach seems to be less adequate. Charge pumping and fast transient measurements were conducted on HfSixOy (20% SiO2) and 'hybrid stack' (HfO2/ HfSixOy) gate dielectrics to investigate the effects of trapped charge on device performance (i.e., mobility). The HfSixOy films were deposited at 2 Torr and 4 Torr and were subjected to various post deposition anneal (PDA) ambients and temperatures. 4 Torr silicates exhibit a higher mobility (peak and high field) than 2 Torr silicates that were subjected to the same post deposition processes. The impact of interfacial and bulk high-k properties on charge trapping issues was investigated using hybrid gate dielectric stacks of varying physical thickness with polysilicon electrodes. FA CP gives low interface state densities for all depositions indicating good interface passivation, whereas VA CP and fast transient shows large trap densities in the bulk of the high-k layer. Results demonstrate that the bulk trapping in the high-k film contributes to the degradation of device performance. Using fast transient measurements and analysis, trapped charge and free-carrier mobility can be extracted allowing characterization of the 'trap free' mobility, which is quite close to the universal electron mobility curve in the high field regime for process conditions of interest.