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This thesis proposes optimisation methods for improving the performance of circuits imple- mented on a custom reconfigurable hardware platform with knowledge of intrinsic variations, through the use of digital reconfiguration. With the continuing trend of transistor shrinking, stochastic variations become first order effects, posing a significant challenge for device reliability. Traditional device models tend to be too conservative, as the margins are greatly increased to account for these variations. Variation-aware optimisation methods are then required to reduce the performance spread caused by these substrate variations. The Programmable Analogue and Digital Array (PAnDA) is a reconfigurable hardware plat- form which combines the traditional architecture of a Field Programmable Gate Array (FPGA) with the concept of configurable transistor widths, and is used in this thesis as a platform on which variability-aware circuits can be implemented. A model of the PAnDA architecture is designed to allow for rapid prototyping of devices, making the study of the effects of intrinsic variability on circuit performance – which re- quires expensive statistical simulations – feasible. This is achieved by means of importing statistically-enhanced transistor performance data from RandomSPICE simulations into a model of the PAnDA architecture implemented in hardware. Digital reconfiguration is then used to explore the hardware resources available for performance optimisation. A bio-inspired optimisation algorithm is used to explore the large solution space more efficiently. Results from test circuits suggest that variation-aware optimisation can provide a significant reduction in the spread of the distribution of performance across various instances of circuits, as well as an increase in performance for each. Even if transistor geometry flexibility is not available, as is the case of traditional architectures, it is still possible to make use of the substrate variations to reduce spread and increase performance by means of function relocation.

This thesis proposes a reconfigurable computing approach for supporting parallel processing in large-scale graph traversal algorithms. Our approach is based on a reconfigurable hardware architecture which exploits the capabilities of both FPGAs (Field-Programmable Gate Arrays) and a multi-bank parallel memory subsystem. The proposed methodology to accelerate graph traversal algorithms has been applied to three case studies, revealing that application-specific hardware customisations can benefit performance. A summary of our four contributions is as follows. First, a reconfigurable computing approach to accelerate large-scale graph traversal algorithms. We propose a reconfigurable hardware architecture which decouples computation and communication while keeping multiple memory requests in flight at any given time, taking advantage of the high bandwidth of multi-bank memory subsystems. Second, a demonstration of the effectiveness of our approach through two case studies: the breadth-first search algorithm, and a graphlet counting algorithm from bioinformatics. Both case studies involve graph traversal, but each of them adopts a different graph data representation. Third, a method for using on-chip memory resources in FPGAs to reduce off-chip memory accesses for accelerating graph traversal algorithms, through a case-study of the All-Pairs Shortest-Paths algorithm. This case study has been applied to process human brain network data. Fourth, an evaluation of an approach based on instruction-set extension for FPGA design against many-core GPUs (Graphics Processing Units), based on a set of benchmarks with different memory access characteristics. It is shown that while GPUs excel at streaming applications, the proposed approach can outperform GPUs in applications with poor locality characteristics, such as graph traversal problems.

Embedded electronics are widely employed in cyber-physical systems (CPSes), which tightly integrate and coordinate computational and physical elements. CPSes are extensively deployed in security-critical applications and nationwide infrastructure. Perimeter security approaches to preventing malware infiltration of CPSes are challenged by the complexity of modern embedded systems incorporating numerous heterogeneous and updatable components. Global supply chains and third-party hardware components, tools, and software limit the reach of design verification techniques and introduce security concerns about deliberate Trojan inclusions. As a consequence, skilled attacks against CPSes have demonstrated that these systems can be surreptitiously compromised. Existing run-time security approaches are not adequate to counter such threats because of either the impact on performance and cost, lack of scalability and generality, trust needed in global third parties, or significant changes required to the design flow. We present a protection scheme called Run-time Enhancement of Trusted Computing (RETC) to enhance trust in CPSes containing untrusted software and hardware. RETC is complementary to design-time verification approaches and serves as a last line of defense against the rising number of inexorable threats against CPSes. We target systems built using reconfigurable hardware to meet the flexibility and high-performance requirements of modern security protections. Security policies are derived from the system physical characteristics and component operational specifications and translated into synthesizable hardware integrated into specific interfaces on a per-module or per-function basis. The policy-based approach addresses many security challenges by decoupling policies from system-specific implementations and optimizations, and minimizes changes required to the design flow. Interface guards enable in-line monitoring and enforcement of critical system computations at run-time. Trust is only required in a small set of simple, self-contained, and verifiable guard components. Hardware trust anchors simultaneously addresses the performance, flexibility, developer productivity, and security requirements of contemporary CPSes. We apply RETC to several CPSes having common security challenges including: secure reconfiguration control in reconfigurable cognitive radio platforms, tolerating hardware Trojan threats in third-party IP cores, and preserving stability in process control systems. High-level architectures demonstrated with prototypes are presented for the selected applications. Implementation results illustrate the RETC efficiency in terms of the performance and overheads of the hardware trust anchors. Testbenches associated with the addressed threat models are generated and experimentally validated on reconfigurable platform to establish the protection scheme efficacy in thwarting the selected threats. This new approach significantly enhances trust in CPSes containing untrusted components without sacrificing cost and performance.

Twenty-first century Field-Programmable Gate Arrays (FPGAs) are no longer used for implementing simple “glue logic” functions. They have become complex arrays of reconfigurable logic resources and memories as well as highly optimised functional blocks, capable of implementing large systems on a single chip. Moreover, Dynamic Partial Reconfiguration (DPR) capability permits to adjust some logic resources on the chip at runtime, whilst the rest are still performing active computations. During the last few years, DPR has become a hot research topic with the objective of building more reliable, efficient and powerful electronic systems. For instance, DPR can be used to mitigate spontaneously occurring bit upsets provoked by radiation, or to jiggle around the FPGA resources which progressively get damaged as the silicon ages. Moreover, DPR is the enabling technology for a new computing paradigm which combines computation in time and space. In Reconfigurable Computing (RC), a battery of computation-specific circuits (“hardware tasks”) are swapped in and out of the FPGA on demand to hold a continuous stream of input operands, computation and output results. Multitasking, adaptation and specialisation are key properties in RC, as multiple swappable tasks can run concurrently at different positions on chip, each with custom data-paths for efficient execution of specific computations. As a result, considerable computational throughput can be achieved even at low clock frequencies. However, DPR penetration in the commercial market is still testimonial, mainly due to the lack of suitable high-level design tools to exploit this technology. Indeed, currently, special skills are required to successfully develop a dynamically reconfigurable application. In light of the above, this thesis aims at bridging the gap between high-level application and low-level DPR technology. Its main objective is to develop Operating System (OS)-like support for high-level software-centric application developers in order to exploit the benefits brought about by DPR technology, without having to deal with the complex low-level hardware details. The developed solution in this thesis is named as R3TOS, which stands for Reliable Reconfigurable Real-Time Operating System. R3TOS defines a flexible infrastructure for reliably executing reconfigurable hardware-based applications under real-time constraints. In R3TOS, the hardware tasks are scheduled in order to meet their computation deadlines and allocated to non-damaged resources, keeping the system fault-free at all times. In addition, R3TOS envisages a computing framework whereby both hardware and software tasks coexist in a seamless manner, allowing the user to access the advanced computation capabilities of modern reconfigurable hardware from a software “look and feel” environment. This thesis covers all of the design and implementation aspects of R3TOS. The thesis proposes a novel EDF-based scheduling algorithm, two novel task allocation heuristics (EAC and EVC) and a novel task allocation strategy (called Snake), addressing many RC-related particularities as well as technological constraints imposed by current FPGA technology. Empirical results show that these approaches improve on the state of the art. Besides, the thesis describes a novel way to harness the internal reconfiguration mechanism of modern FPGAs to performinter-task communications and synchronisation regardless of the physical location of tasks on-chip. This paves the way for implementing more sophisticated RC solutions which were only possible in theory in the past. The thesis illustrates R3TOS through a proof-of-concept prototype with two demonstrator applications: (1) dependability oriented control of the power chain of a railway traction vehicle, and (2) datastreaming oriented Software Defined Radio (SDR).

Complex Systems can be seen in many important events and aspects of our world. However, their study is not a trivial task due to the multiple complications found to access some of these systems, the complex and convoluted network of connections between elements and the amount of elements involved in them. This study also affects engineered systems, which have become more complex due to an increase in their size and number of interactions between their elements, resulting in unexpected misbehaviour that may potentially alter the results of the system. A traditional top-down analytical approach is not enough to completely understand Complex Systems, and a bottom-up agent-based approach has been suggested to be used to model and simulate them. Reconfigurable Hardware represents a suitable platform for the natural implementation of Agent-based Systems, used in the simulations of Complex Systems, providing the parallelism and flexibility that other platforms lack. The main aim of the work in this thesis is to present a study of how to implement and what are the benefits of implementing Agent-based System using Reconfigurable Hardware. A static implementation takes advantage of the parallelism and flexibility of Reconfigurable Hardware to implement Agent-based Systems, using a flexible decentralised communication structure, which provides the elements of the system with the required level of flexibility in their interactions. A suitable communication structure simplifies the behaviour of the processing elements. A dynamic implementation exploits dynamic reconfiguration in order to create a dynamic architecture, which facilitates the implementation of the dynamic behaviour of the agents by adapting to changes in their interactions. The communication between elements is simplified and the efficiency and flexibility of the system increases. This thesis presents the suitability of both implementations in the design of simulations of Complex Systems, exploiting the parallelism and flexibility of Reconfigurable Hardware, using Reynolds' Boids as case study, and highlight the advantages and disadvantages of each approach.

Speeding up backtracing will result in improving the efficiency of many CAD and test algorithms. In this research, we propose the architecture of a new backtracing solver using reconfigurable hardware and a virtual logic scheme. Our main contributions include new forms of massive fine-grain parallelism, structured design techniques that multiple backtrace all paths in a multiple-level combinational circuit. To support the multiple backtrace technique, we propose a circuit decomposition algorithm, new circuit models, and objectives with different priorities. The circuit decomposition technique is also the basis of the virtual logic scheme, since it allow to solve problems that exceed the hardware capacity. We improve the controllability measurement and representation method. Thus, controllability can be implemented in hardware to guide the backtracing process and avoid the detrimental decisions. Our architecture is easily scalable. Our results show significant speedup in large size benchmarks when compared with a prior SAT solver for the combinational backtracing problem.

Reconfigurable hardware systems offer great potential for improving performance over software through increased parallelism and reduced control overhead. However, the configuration of the hardware is performed statically, restricting the system's ability to adapt to the run-time environment. Thisthesis explores the possibility ot compiling from object code into a reconfigurable hardware structure at run-time to allow the hardware configuration to benefit from the behaviour of the currently executing code.

This thesis proposes novel algorithm and hardware optimisation approaches to accelerate Deep Neural Networks (DNNs), including both Convolutional Neural Networks (CNNs) and Bayesian Neural Networks (BayesNNs). The first contribution of this thesis is to propose an adaptable and reconfigurable hardware design to accelerate CNNs. By analysing the computational patterns of different CNNs, a unified hardware architecture is proposed for both 2-Dimension and 3-Dimension CNNs. The accelerator is also designed with runtime adaptability, which adopts different parallelism strategies for different convolutional layers at runtime. The second contribution of this thesis is to propose a novel neural network architecture and hardware design co-optimisation approach, which improves the performance of CNNs at both algorithm and hardware levels. Our proposed three-phase co-design framework decouples network training from design space exploration, which significantly reduces the time-cost of the co-optimisation process. The third contribution of this thesis is to propose an algorithmic and hardware co-optimisation framework for accelerating BayesNNs. At the algorithmic level, three categories of structured sparsity are explored to reduce the computational complexity of BayesNNs. At the hardware level, we propose a novel hardware architecture with the aim of exploiting the structured sparsity for BayesNNs. Both algorithmic and hardware optimisations are jointly applied to push the performance limit.

Biomedical implant-scale electronics have gained a lot of attention in recent years. Particularly, neuromodulation implants are an important tool in treating drug-resistant neurological conditions, while also improving our understanding of the brain. Although demands for adding more functionality to the implant are constantly increasing, their power consumption and size are usually limiting factors that determine longevity of the battery and dictates the overall throughput of brain data. Therefore, in order to gain more insight into brain dynamics while keeping device small, it is crucial to increase number of accessing channels and to improve the overall device efficiency. Enabling better platform technologies that would greatly impact the field of neuroscience and enhance the quality of life of patients with neurological disorders is a difficult task. This work seeks to address some of the design challenges related to a variety of biomedical applications, while providing the power efficiency and flexibility needed for implantable devices.First, a new self-powered, thermo-electric harvesting architecture is proposed and demonstrated. The miniaturized system, accompanied with efficient energy processing circuits was able to achieve a cold startup with a few 10's of mV of input voltage while achieving good end-to-end efficiency. This design was further verified in real environment (in-vivo, rat) and showed a good trade-off between the form factor and extracted power.Second, we demonstrated a 'holy grail' implant-scale neuromodulation interface with high linear input range that enables concurrent sensing and stimulation. Our 64-channel interface meets the requirements of human-quality implants at an unprecedented level of electronic miniaturization as compared to prior art. It offers major new clinical perspectives: it supports different power delivery options, always-on sensing for enhanced closed-loop therapy, multi-channel arbitrary stimulation waveforms with user-friendly programming, high-resolution neural interface for more precise target localization.Finally, a new neural recording paradigm based on the fast calcium imaging is described. This technology can provide communication between the brain and the external world at the resolution of individual neurons. We propose a hardware friendly approach for analyzing 1000's of neurons in a single pipeline and in real-time, while relaxing the memory and computational requirements. This method is capable of delivering two orders of magnitude higher brain coverage as compared to the state-of-the-art electrophysiological approach, leading to a high-resolution, high-data-rate neural interface.

Conditions such as hypoxic-ischaemic encephalopathy (HIE) and perinatal arterial ischaemic stroke (PAIS) are causes of lifelong neurodisability in a few hundred infants born in the UK each year. Early diagnosis and treatment are key, but no effective bedside detection and monitoring technology is available. Non-invasive, near-infrared techniques have been explored for several decades, but progress has been inhibited by the lack of a portable technology, and intensity measurements, which are strongly sensitive to uncertain and variable coupling of light sources and detector to the scalp. A technique known as time domain diffuse optical tomography (TD-DOT) uses measurements of photon flight times between sources and detectors placed on the scalp. Mean flight time is largely insensitive to the coupling and variation in mean flight time can reveal spatial variation in blood volume and oxygenation in regions of brain sampled by the measurements. While the cost, size and high power consumption of such technology have hitherto prevented development of a portable imaging system, recent advances in silicon technology are enabling portable and low-power TD-DOT devices to be built. A prototype TD-DOT system is proposed and demonstrated, with the long-term aim to design a portable system based on independent modules, each supporting a time-of-flight detector and a pulsed source. The operation is demonstrated of components that can be integrated in a portable system: silicon photodetectors, integrated circuit-based signal conditioning and time detection -- built using a combination of off-the-shelf components and reconfigurable hardware, standard computer interfaces, and data acquisition and calibration software. The only external elements are a PC and a pulsed laser source. This thesis describes the design process, and results are reported on the performance of a 2-channel system with online histogram generation, used for phantom imaging. Possible future development of the hardware is also discussed.

We are experiencing a new industrial revolution, a cyber-physical systems revolution. The Internet of Things (IoT) is at the core of this development, and it is changing the way we perceive the world around us, impacting both business and technology. Smart cars, smart thermostats, home automation hubs, smart lighting, and smart weather stations are common technologies met in most cities and households. The number of these devices is going to increase even more, and it is predicted to reach billions over the next few years. Although the IoT technology has reached maturity, we are still unprepared for the large number of devices predicted to reach the world in the near future. Managing high numbers of IoT devices requires stable infrastructures for deployment and management. It also requires creating sustainable infrastructures to minimise the impact on the environment. In this thesis, we hypothesise that using flexible, open, modular, and reconfigurable hardware and software architectures at the base of smart city infrastructure can increase device longevity and minimise device management complexity at scale, while promoting sustainable development. The main contributions are: (1) identification of design requirements for building the next generation IoT device (2) reference architecture for flexible, modular IoT devices, (3) a novel, modular, open-source sensor board for building plug-and-play smart devices, allowing for complete removal/replacement of sensors and computing module, (4) a novel, modular, open-source software architecture, including: minimal Operating System (OS), over the air (OTA) updates, containerisation and remote device management, and (5) demonstration using a real-life application of environmental monitoring. The reference architecture presented in this thesis provides a robust, persistent, and reliable long-term solution for IoT deployements that addresses concerns regarding the negative impact of IoT on long term sustainable development.

As the technology node size for integrated circuit (IC) designs decreases, the cost of building and maintaining an IC foundry rapidly increases. Companies unable to afford local manufacturing have become reliant on outsourcing the physical manufacturing process. This introduces confidentiality, integrity, and authenticity security vulnerabilities into the IC design lifecycle. Even companies that manufacture in-house and use field-programmable gate array (FPGA) chips may require third-party system integrators to assemble the final product. When said product is sent to a third-party foundry or system integrator, the embodied IC/FPGA circuitry is susceptible to IP theft, Trojan insertion, and reverse engineering (RE) attacks. To address this, we realize a novel approach to sequential logic locking, FSMLock, that conceals a finite state machine's (FSM) output and next-state logic through classical encryption. The FSM is abstracted as the configuration data for a lookup table (LUT), encrypted with a chip-specific (individual) internal key, and stored in the newly mandated non-volatile memory (NVM). The configuration data is then decrypted in blocks and loaded into the in-scope random access memory (RAM) when required. Doing so locks the sequential FSM logic and conceals its functionality from third-party foundries and system integrators, system design engineers with access to the post-locked hardware description language (HDL) files, and end-users with production units. FSMLock has applications in reconfigurable hardware, such as FPGAs, even when no third-party access is initially required. In older and low-cost FPGA devices with externally stored bitstream configurations, the absence of trusted bitstream encryption/authentication means that if the bitstream is recovered from the external memory device, an adversary can reconstruct and modify the original design functionality. FSMLock can improve the security of such FPGA chips by storing targeted FSM logic in encrypted NVM. Therefore, a breach of the bitstream contents and the NVM's individual internal key would be required to compromise the security of the targeted sequential circuitry. Further, if a key preprocessor utilizing a physically unclonable function (PUF) is included to discriminate the boundary level (chip) key from the internal key, the confidentiality of the locked circuit is assured, even considering the disclosure of a chip key with its paired encrypted NVM configuration. For the scope of this thesis, we sought to develop an automated software toolset capable of translating pre-partitioned FSMs into encrypted memory configurations. When the configuration is combined with the provided HDL entity responsible for run-time decryption and scope control, a locked HDL model of the FSM, i.e., the FSMLock primitive, is formed.

Field Programmable Gate Array (FPGA) devices offer a suitable platform for survivable hardware architectures in mission-critical systems. In this dissertation, active dynamic redundancy-based fault-handling techniques are proposed which exploit the dynamic partial reconfiguration capability of SRAM-based FPGAs. Self-adaptation is realized by employing reconfiguration in detection, diagnosis, and recovery phases. To extend these concepts to semiconductor aging and process variation in the deep submicron era, resilient adaptable processing systems are sought to maintain quality and throughput requirements despite the vulnerabilities of the underlying computational devices. A new approach to autonomous fault-handling which addresses these goals is developed using only a uniplex hardware arrangement. It operates by observing a health metric to achieve Fault Demotion using Recon- figurable Slack (FaDReS). Here an autonomous fault isolation scheme is employed which neither requires test vectors nor suspends the computational throughput, but instead observes the value of a health metric based on runtime input. The deterministic flow of the fault isolation scheme guarantees success in a bounded number of reconfigurations of the FPGA fabric. FaDReS is then extended to the Priority Using Resource Escalation (PURE) online redundancy scheme which considers fault-isolation latency and throughput trade-offs under a dynamic spare arrangement. While deep-submicron designs introduce new challenges, use of adaptive techniques are seen to provide several promising avenues for improving resilience. The scheme developed is demonstrated by hardware design of various signal processing circuits and their implementation on a Xilinx Virtex-4 FPGA device. These include a Discrete Cosine Transform (DCT) core, Motion Estimation (ME) engine, Finite Impulse Response (FIR) Filter, Support Vector Machine (SVM), and Advanced Encryption Standard (AES) blocks in addition to MCNC benchmark circuits. A iii significant reduction in power consumption is achieved ranging from 83% for low motion-activity scenes to 12.5% for high motion activity video scenes in a novel ME engine configuration. For a typical benchmark video sequence, PURE is shown to maintain a PSNR baseline near 32dB. The diagnosability, reconfiguration latency, and resource overhead of each approach is analyzed. Compared to previous alternatives, PURE maintains a PSNR within a difference of 4.02dB to 6.67dB from the fault-free baseline by escalating healthy resources to higher-priority signal processing functions. The results indicate the benefits of priority-aware resiliency over conventional redundancy approaches in terms of fault-recovery, power consumption, and resource-area requirements. Together, these provide a broad range of strategies to achieve autonomous recovery of reconfigurable logic devices under a variety of constraints, operating conditions, and optimization criteria.

To achieve faster computation rates using cluster computers, reconfigurable resources are beginning to be utilized in computations. The Finite-Difference Time-Domain (FDTD) is a powerful method to solve differential equations that can be easily pipelined and placed into a Field Programmable Gate Array (FPGA) on a cluster. In this thesis, I show that the FPGA can be used to speed up a two dimensional simulation of a single precision FDTD computation on a cluster. One system demonstrated that the computation rate was two to four times faster when considered by itself; however, the means to transfers the data took more than 28 times the computation rate. A second system compared the full executable time of the program with hardware rates comparable to the software speed. Different methods of transferring the data were also tested. Overall, this shows that improvements can be made utilizing the reconfigurable resource to assist in the computation.

Designing high-performance, fault-tolerant multisensory electronic systems for hostile environments such as nuclear plants and outer space within the constraints of cost, power and flexibility is challenging. Issues such as ionizing radiation, extreme temperature and ageing can lead to faults in the electronics of these systems. In addition, the remote nature of these environments demands a level of flexibility and autonomy in their operations. The standard practice of using specially hardened electronic devices for such systems is not only very expensive but also has limited flexibility. This thesis proposes novel techniques that promote the use of Commercial Off-The- Shelf (COTS) reconfigurable devices to meet the challenges of high-performance systems for hostile environments. Reconfigurable hardware such as Field Programmable Gate Arrays (FPGA) have a unique combination of flexibility and high performance. The flexibility offered through features such as dynamic partial reconfiguration (DPR) can be harnessed not only to achieve cost-effective designs as a smaller area can be used to execute multiple tasks, but also to improve the reliability of a system as a circuit on one portion of the device can be physically relocated to another portion in the case of fault occurrence. However, to harness these potentials for high performance and reliability in a cost-effective manner, novel runtime management tools are required. Most runtime support tools for reconfigurable devices are based on ideal models which do not adequately consider the limitations of realistic FPGAs, in particular modern FPGAs which are increasingly heterogeneous. Specifically, these tools lack efficient mechanisms for ensuring a high utilization of FPGA resources, including the FPGA area and the configuration port and clocking resources, in a reliable manner. To ensure high utilization of reconfigurable device area, placement management is a key aspect of these tools. This thesis presents novel techniques for the management of hardware task placement on COTS reconfigurable devices for high performance and reliability. To this end, it addresses design-time issues that affect efficient hardware task placement, with a focus on reliability. It also presents techniques to maximize the utilization of the FPGA area in runtime, including techniques to minimize fragmentation. Fragmentation leads to the creation of unusable areas due to dynamic placement of tasks and the heterogeneity of the resources on the chip. Moreover, this thesis also presents an efficient task reuse mechanism to improve the availability of the internal configuration infrastructure of the FPGA for critical responsibilities like error mitigation. The task reuse scheme, unlike previous approaches, also improves the utilization of the chip area by offering defragmentation. Task relocation, which involves changing the physical location of circuits is a technique for error mitigation and high performance. Hence, this thesis also provides a functionality-based relocation mechanism for improving the number of locations to which tasks can be relocated on heterogeneous FPGAs. As tasks are relocated, clock networks need to be routed to them. As such, a reliability-aware technique of clock network routing to tasks after placement is also proposed. Finally, this thesis offers a prototype implementation and characterization of a placement management system (PMS) which is an integration of the aforementioned techniques. The performance of most of the proposed techniques are tested using data processing tasks of a NASA JPL spectrometer application. The results show that the proposed techniques have potentials to improve the reliability and performance of applications in hostile environment compared to state-of-the-art techniques. The task optimization technique presented leads to better capacity to circumvent permanent faults on COTS FPGAs compared to state-of-the-art approaches (48.6% more errors were circumvented for the JPL spectrometer application). The proposed task reuse scheme leads to approximately 29% saving in the amount of configuration time. This frees up the internal configuration interface for more error mitigation operations. In addition, the proposed PMS has a worst-case latency of less than 50% of that of state-of- the-art runtime placement systems, while maintaining the same level of placement quality and resource overhead.

Physics is experiencing an exciting period of exploration into the nature of dark energy, dark matter, and gravitation. With 95% of the mass-energy of the Universe still unexplained, the answers to many further fundamental questions of astro-, theoretical- and particle-physics are being hampered. In the coming years, DES, HSC, KiDS, Euclid and LSST will image billions of galaxies, aiming to use observational data from the late Universe to infer cosmological parameters and compare cosmological models. One of the most promising observables is the weak gravitational lensing effect. Using the statistical power from many small distortions, called shear, DES has provided excellent constraints. However, the standard 2-point statistics do not capture the full information in the data. In the late Universe, gravitational collapse has led to a highly non-Gaussian density field, for which 2-point correlations are not a unique statistical description, and even all N-point functions cannot completely characterize. The research presented in this thesis focuses on methods to reconstruct mass maps from DES weak lensing data and using map-based statistics to infer cosmological parameters and assess theoretical models in a principled Bayesian framework. In Chapter 2, I compare three mass mapping methods with closed-form priors using DES SV data and simulations. In Chapter 3, I demonstrate how the Wiener filter (one of the above methods) computation can be sped up by an order of magnitude using Dataflow Engines (reconfigurable hardware). In Chapter 4, I present a Bayesian hierarchical model which takes into account added uncertainty introduced when noisy simulations are used to generate theoretical predictions. In Chapter 5, with my publicly available DeepMass code, I demonstrate how mass maps reconstructions can be improved (> 10% mean-square-error compared with previously presented methods) using deep learning techniques trained on simulations. In Chapter 6, I discuss future work and the applicability of likelihood-free inference methods for map-based statistics.

Network performance has contributed fundamentally to the growth of supercomputing over the past decades. In parallel, High Performance Computing (HPC) peak performance has depended, first, on ever faster/denser CPUs, and then, just on increasing density alone. As operating frequency, and now feature size, have levelled off, two new approaches are becoming central to achieving higher net performance: configurability and integration. Configurability enables hardware to map to the application, as well as vice versa. Integration enables system components that have generally been single function-e.g., a network to transport data—to have additional functionality, e.g., also to operate on that data. More generally, integration enables compute-everywhere: not just in CPU and accelerator, but also in network and, more specifically, the communication switches. In this thesis, we propose four novel methods of enhancing HPC performance through Advanced Computing in the Switch (ACiS). More specifically, we propose various flexible and application-aware accelerators that can be embedded into or attached to existing communication switches to improve the performance and scalability of HPC and Machine Learning (ML) applications. We follow a modular design discipline through introducing composable plugins to successively add ACiS capabilities. In the first work, we propose an inline accelerator to communication switches for user-definable collective operations. MPI collective operations can often be performance killers in HPC applications; we seek to solve this bottleneck by offloading them to reconfigurable hardware within the switch itself. We also introduce a novel mechanism that enables the hardware to support MPI communicators of arbitrary shape and that is scalable to very large systems. In the second work, we propose a look-aside accelerator for communication switches that is capable of processing packets at line-rate. Functions requiring loops and states are addressed in this method. The proposed in-switch accelerator is based on a RISC-V compatible Coarse Grained Reconfigurable Arrays (CGRAs). To facilitate usability, we have developed a framework to compile user-provided C/C++ codes to appropriate back-end instructions for configuring the accelerator. In the third work, we extend ACiS to support fused collectives and the combining of collectives with map operations. We observe that there is an opportunity of fusing communication (collectives) with computation. Since the computation can vary for different applications, ACiS support should be programmable in this method. In the fourth work, we propose that switches with ACiS support can control and manage the execution of applications, i.e., that the switch be an active device with decision-making capabilities. Switches have a central view of the network; they can collect telemetry information and monitor application behavior and then use this information for control, decision-making, and coordination of nodes. We evaluate the feasibility of ACiS through extensive RTL-based simulation as well as deployment in an open-access cloud infrastructure. Using this simulation framework, when considering a Graph Convolutional Network (GCN) application as a case study, a speedup of on average 3.4x across five real-world datasets is achieved on 24 nodes compared to a CPU cluster without ACiS capabilities.

Genetic Algorithms (GAs) are a class of numerical and combinatorial optimisers which are especially useful for solving non-linear and non-convex problems. However, the required execution time often limits their application to small-scale or latency-insensitive problems, so techniques to increase the speed and computational efficiency of GAs are needed. FPGA-based acceleration has significant potential for speeding up genetic algorithms, but existing FPGA-based GA systems are limited by the need for extensive hardware architecture customisation by end users and the relatively small improvement in performance. The main reasons for these limitations are that most of the units in these GA systems are fixed and the algorithms of these FPGA-based systems are just inherited from software GAs without making full use of reconfigurable hardware. This thesis examines the previous work and then rethinks the creation of genetic algorithms with reconfigurable computing, and aims to address the problems of low-level programmability, flexibility, and performance in current GA systems. The thesis first presents a general-purpose automated framework for creating and executing a flexible parallel GA system on one FPGA or even multiple FPGAs, which increases the flexibility in GA architecture and removes the low-level hardware programmability barrier for non-expert users. The thesis then proposes a novel hardware-oriented approach called Pipelined Genetic Propagation (PGP), which is intrinsically spatially distributed and fully pipelined. PGP represents a GA solver as a graph of loosely coupled genetic operators, which allows the system to be scaled to the available resources, and also to dynamically change connection topology at run-time to explore different strategies. Finally the thesis extends PGP in three ways: Recursive PGP for multiple level optimisation problems, machine learning guided PGP for automatically changing the connection topology, and partially reconfigurable PGP to increase flexibility. Overall, the thesis presents new ways to perform genetic algorithms in reconfigurable computing, with high-level programmability, sufficient flexibility and high performance.

Neural prostheses that stimulate the neocortex utilizing electrical stimulation via implantable electrodes have been used to treat a wide range of neurological and psychological disorders. However, fundamental limitations of implantable electrodes have limited the prosthesis effectiveness as there remains concerns over their long-term stimulation efficacy and inability to create precise patterns of neural activity. Latest developments in micro-magnetic technology have shown that magnetic stimulation from micro-coil-based neural probes is capable of modulating neural behavior while circumventing the limitations of implantable electrodes. This is due to the induced electric fields from magnetic stimulation being spatially asymmetric, avoiding the simultaneous stimulation of passing axons, as well magnetic fields having high permeability to biological substances, allowing for complete device encapsulation. While these devices have been shown to modulate neural activity in both in vitro and in vivo experiments, the lack of reconfigurable hardware on the probe fixes the location of the neurostimulation sites post-implantation. This works explores how co-designing CMOS circuitry, micro-coil design, and nanofabrication processing can be used to fabricate the next generation of micro-coil-based neural probes, capable of spatially programmable micro-magnetic neurostimulation.

Current FPGAs can implement large systems because of the high density of reconfigurable logic resources in a single chip. FPGAs are comprehensive devices that combine flexibility and high performance in the same platform compared to other platform such as General-Purpose Processors (GPPs) and Application Specific Integrated Circuits (ASICs). The flexibility of modern FPGAs is further enhanced by introducing Dynamic Partial Reconfiguration (DPR) feature, which allows for changing the functionality of part of the system while other parts are functioning. FPGAs became an important platform for digital image processing applications because of the aforementioned features. They can fulfil the need of efficient and flexible platforms that execute imaging tasks efficiently as well as the reliably with low power, high performance and high flexibility. The use of FPGAs as accelerators for image processing outperforms most of the current solutions. Current FPGA solutions can to load part of the imaging application that needs high computational power on dedicated reconfigurable hardware accelerators while other parts are working on the traditional solution to increase the system performance. Moreover, the use of the DPR feature enhances the flexibility of image processing further by swapping accelerators in and out at run-time. The use of fault mitigation techniques in FPGAs enables imaging applications to operate in harsh environments following the fact that FPGAs are sensitive to radiation and extreme conditions. The aim of this thesis is to present a platform for efficient implementations of imaging tasks. The research uses FPGAs as the key component of this platform and uses the concept of DPR to increase the performance, flexibility, to reduce the power dissipation and to expand the cycle of possible imaging applications. In this context, it proposes the use of FPGAs to accelerate the Image Processing Pipeline (IPP) stages, the core part of most imaging devices. The thesis has a number of novel concepts. The first novel concept is the use of FPGA hardware environment and DPR feature to increase the parallelism and achieve high flexibility. The concept also increases the performance and reduces the power consumption and area utilisation. Based on this concept, the following implementations are presented in this thesis: An implementation of Adams Hamilton Demosaicing algorithm for camera colour interpolation, which exploits the FPGA parallelism to outperform other equivalents. In addition, an implementation of Automatic White Balance (AWB), another IPP stage that employs DPR feature to prove the mentioned novelty aspects. Another novel concept in this thesis is presented in chapter 6, which uses DPR feature to develop a novel flexible imaging system that requires less logic and can be implemented in small FPGAs. The system can be employed as a template for any imaging application with no limitation. Moreover, discussed in this thesis is a novel reliable version of the imaging system that adopts novel techniques including scrubbing, Built-In Self Test (BIST), and Triple Modular Redundancy (TMR) to detect and correct errors using the Internal Configuration Access Port (ICAP) primitive. These techniques exploit the datapath-based nature of the implemented imaging system to improve the system's overall reliability. The thesis presents a proposal for integrating the imaging system with the Robust Reliable Reconfigurable Real-Time Heterogeneous Operating System (R4THOS) to get the best out of the system. The proposal shows the suitability of the proposed DPR imaging system to be used as part of the core system of autonomous cars because of its unbounded flexibility. These novel works are presented in a number of publications as shown in section 1.3 later in this thesis.

One of the great advances in computation over the last 20 years is the availability, connectivity, and growth of datacenters. These advances in the datacenter have motivated research, development, and adoption of new techniques to improve the overall performance of datacenter activities. Such techniques include virtualization, software defined networking (SDN), distributed computing, platform-as-a-service (PaaS), serverless computing, and many more. Continued improvements and support for all these datacenter applications has required a re-imagining of the current connected environment into one that is more data focused, where computation is everywhere, and high performance networks connect all resources together. A key part of this evolution is making network fabrics more intelligent by substituting traditional network interface cards (NICs) with SmartNICs; these create opportunities to move computation away from compute nodes and into the network. Field programmable gate arrays (FPGAs) play a significant role in realizing these new opportunities in the network fabric as they have both compute and communication hardware. In this thesis, we investigate performance and usability of network FPGAs and demonstrate their utility with case studies in security and privacy for tenants in the datacenter. We propose an approach to achieve a new level of security and performance through the use of reconfigurable hardware available with network attached FPGA SmartNICs. We first show how FPGAs directly connected to high-bandwidth network resources can reduce the network load through function offload onto FPGAs. We then demonstrate the capabilities of FPGA SmartNICs to perform in-line packet acceleration functions as well as application acceleration without host processing. Next, we improve the security of the datacenter through network isolation techniques and secure data processing between tenants co-located in the same datacenter. To this end, we accelerate a state-of-the-art cryptographic algorithm, Secret Sharing Multi-Party Computation (MPC), using FPGAs. Our FPGA accelerated Secret Sharing MPC uses at least a 10x less computing resources compared to the original design using CPUs. To demonstrate the real-world advantages of leveraging network-attached FPGA SmartNICs, we present three unique applications of these FPGAs specifically for security. First, we improve the performance of datacenter nodes on CPUs by offloading common packet functions such as remote memory access and packet fragmentation. Second, towards the goal of providing private cloud enclaves, we propose a method of securing tenant private networks with FPGA SmartNICs. Finally, we leverage FPGA SmartNICs to efficiently perform joint confidential data processing between cooperating organizations.

The cost of off-chip memory access (in bandwidth, time and energy consumption) has become a major concern in the design of many hardware systems. Due to reasons such as the increasing performance gap between computing engines and memory systems, the process of data acquisition from memory has an increasingly dominant impact to the overall of the system performance. The cost in memory communication bandwidth and time consumption of data acquisition has become more significant, stalling the application and reducing its execution. Energy consumption has also become one of the main concerns to modern hardware systems, especially for embedded applications, and the energy spent on memory accessing has been reported to occupy a large proportion of the overall energy consumption of the system. All these lead to the research topic of reducing the cost of memory access in hardware systems. Particularly for image processing systems, due to the ever growing size of image data, the task of image data acquisition poses an increasing challenge to the design of the systems. Various researches have addressed this problem of image data acquisition by exploiting the characteristics of memory structures and image processing applications. Some methods approach this problem from software perspective, changing for example the source code of the application so that the off-chip memory access is minimized; other methods approach this problem from hardware perspective, modifying the structure of memories and reorganizing the order of data transmission sequences. This thesis provides an alternative way of dealing with this problem and proposes the framework of ``Context-based Image Acquisition'' (CbIA) for hardware systems. Instead of accessing from the off-chip memory all image data requested by the application, the proposed framework accesses only fractions of the image and by utilizing image processing algorithms it reconstructs the missing part. This allows the proposed framework to trade computational effort for reduced cost of memory access, and ultimately trade image quality with reduced overall cost of the image acquisition process. On top of this, the proposed framework has the advantage of being independent from both the memory and the image processing application, and therefore can be seamlessly integrated into existing image processing systems. The thesis elaborates on the proposed framework from both the algorithmic perspective and the hardware architectural perspective. A designed and implemented CbIA architecture is evaluated on reconfigurable hardware, reporting a reduction of up to 88\% of communication bandwidth, 68\% of time consumption, and 50\% of energy consumption of the image acquisition process, at the expense of reduced image quality (about 33 dB of PSNR on chosen benchmark images). Based on this design, this thesis also investigates on more complex algorithms at simulation level for CbIA procedures, including that for generic images as well as for specific image class. The use of more detailed modelling of images and/or domain-specific knowledge improves the ability of the CbIA procedure to trade image quality for bandwidth reduction (an increase of about 2 dB of PSNR with the same bandwidth used), with additional expenses on the computational cost. Finally, the thesis explores the impact brought by the proposed CbIA framework to the future development of hardware system.

Synchronization is a key System-on-Chip (SoC) design issue in modern technologies. As the number of operating points under consideration increases, specifications which are capable of altering key parameters such as the time available for synchronization and Mean Time Between Failures (MTBF) in response to input from the user/system become desirable. This thesis explores how a combination of parallelism and scheduling, referred to as wagging, can be utilized to construct schedulers for synchronizer designs which are capable of pooling the gain-bandwidth products of their composite devices, in order to satisfy this requirement. In this work, we explore the ways in which the areas of graph theory and reconfigurable hardware design can be applied to generate both combinational and sequential scheduler designs, which satisfy the behavior requirement above. Further to this point, this work illustrates that such a scheduler is primarily comprised of an interrupt subsystem, and a reconfigurable token ring. This thesis explores how both of these components can be controlled in absence of a clock signal, as well as the design challenges inherent to each part. The final noteworthy issue in this study is with regard to the flow control of data in a parallel synchronizer that incorporates a First-In First-Out (FIFO) buffer to decouple the reading and writing operations from each other. Such a structure incurs penalties if the data rates on both sides are not well matched. This work presents a method by which combinations of serial and parallel reading operations are used to minimize this mismatch.

There are 285 million people worldwide with a visual impairment, 39 million of whom are completely blind and 246 million partially blind, known as low vision patients. In the UK and other developed countries of the west, retinal dystrophy diseases represent the primary cause of blindness, especially Age Related Macular Degeneration (AMD), diabetic retinopathy and Retinitis Pigmentosa (RP). There are various treatments and aids that can help these visual disorders, such as low vision aids, gene therapy and retinal prosthesis. Retinal prostheses consist of four main stages: the input stage (Image Acquisition), the high level processing stage (Image preparation and retinal encoding), low level processing stage (Stimulation controller) and the output stage (Image displaying on the opto-electronic micro-LEDs array). Up to now, a limited number of full hardware implementations have been available for retinal prosthesis. In this work, a photonic stimulation controller was designed and implemented. The main rule of this controller is to enhance framework results in terms of power and time. It involves, first, an even power distributor, which was used to evenly distribute the power through image sub-frames, to avoid a large surge of power, especially with large arrays. Therefore, the overall framework power results are improved. Second, a pulse encoder was used to select different modes of operation for the opto-electronic micro-LEDs array, and as a result of this the overall time for the framework was improved. The implementation is completed using reconfigurable hardware devices, i.e. Field Programmable Gate Arrays (FPGAs), to achieve high performance at an economical price. Moreover, this FPGA-based framework for an optogenetic retinal prosthesis aims to control the opto-electronic micro-LED array in an efficient way, and to interface and link between the opto-electronic micro-LED array hardware architecture and the previously developed high level retinal prosthesis image processing algorithms.

The increasing commoditization of computers in modern society has exceeded the pace of associated developments in reliability. Although theoretical computer science has advanced greatly in the last thirty years, many of the best techniques have yet to find their way into embedded computers, and their failure can have a great potential for disrupting society. This dissertation presents some approaches to improve computer reliability using software and hardware techniques, and makes the following claims for novelty: innovative development of a toolchain and libraries to support extraction from dependent type checking in a theorem prover; conceptual design and deployment in reconfigurable hardware; an extension of static type-safety to hardware description language and FPGA level; elimination of legacy C code from the target and toolchain; a novel hardware error detection scheme is described and compared with conventional triple modular redundancy. The elimination of any user control of memory management promotes robustness against buffer overruns, and consequently prevents vulnerability to common Trojan techniques. The methodology identifies type punning as a key weakness of commonly encountered embedded languages such as C, in particular the extreme difficulty of determining if an array access is in bounds, or if dynamic memory has been properly allocated and released. A method of eliminating dependence on type-unsafe libraries is presented, in conjunction with code that has optionally been proved correct according to user-defined criteria. An appropriately defined subset of OCaml is chosen with support for the Coq theorem prover in mind, and then evaluated with a custom backend that supports behavioural Verilog, as well as a fixed execution unit and associated control store. Results are presented for this alternative platform for reliable embedded systems development that may be used in future industrial flows. To provide assurance of correct operation, the proven software needs to be executed in an environment where errors are checked and corrected in conjunction with appropriate exception processing in the event of an uncorrectable error. Therefore, the present author’s previously published error detection scheme based on dual-rail logic and self-checking checkers is further developed and compared with traditional N-modular redundancy.

Modern Field-Programmable Gate Arrays (FPGAs) are no longer used to implement small “glue logic” circuitries. The high-density of reconfigurable logic resources in today’s FPGAs enable the implementation of large systems in a single chip. FPGAs are highly flexible devices; their functionality can be altered by simply loading a new binary file in their configuration memory. While the flexibility of FPGAs is comparable to General-Purpose Processors (GPPs), in the sense that different functions can be performed using the same hardware, the performance gain that can be achieved using FPGAs can be orders of magnitudes higher as FPGAs offer the ability for customisation of parallel computational architectures. Dynamic Partial Reconfiguration (DPR) allows for changing the functionality of certain blocks on the chip while the rest of the FPGA is operational. DPR has sparked the interest of researchers to explore new computational platforms where computational tasks are off-loaded from a main CPU to be executed using dedicated reconfigurable hardware accelerators configured on demand at run-time. By having a battery of custom accelerators which can be swapped in and out of the FPGA at runtime, a higher computational density can be achieved compared to static systems where the accelerators are bound to fixed locations within the chip. Furthermore, the ability of relocating these accelerators across several locations on the chip allows for the implementation of adaptive systems which can mitigate emerging faults in the FPGA chip when operating in harsh environments. By porting the appropriate fault mitigation techniques in such computational platforms, the advantages of FPGAs can be harnessed in different applications in space and military electronics where FPGAs are usually seen as unreliable devices due to their sensitivity to radiation and extreme environmental conditions. In light of the above, this thesis investigates the deployment of DPR as: 1) a method for enhancing performance by efficient exploitation of the FPGA resources, and 2) a method for enhancing the reliability of systems intended to operate in harsh environments. Achieving optimal performance in such systems requires an efficient internal configuration management system to manage the reconfiguration and execution of the reconfigurable modules in the FPGA. In addition, the system needs to support “fault-resilience” features by integrating parameterisable fault detection and recovery capabilities to meet the reliability standard of fault-tolerant applications. This thesis addresses all the design and implementation aspects of an Internal Configuration Manger (ICM) which supports a novel bitstream relocation model to enable the placement of relocatable accelerators across several locations on the FPGA chip. In addition to supporting all the configuration capabilities required to implement a Reconfigurable Operating System (ROS), the proposed ICM also supports the novel multiple-clone configuration technique which allows for cloning several instances of the same hardware accelerator at the same time resulting in much shorter configuration time compared to traditional configuration techniques. A faulttolerant (FT) version of the proposed ICM which supports a comprehensive faultrecovery scheme is also introduced in this thesis. The proposed FT-ICM is designed with a much smaller area footprint compared to Triple Modular Redundancy (TMR) hardening techniques while keeping a comparable level of fault-resilience. The capabilities of the proposed ICM system are demonstrated with two novel applications. The first application demonstrates a proof-of-concept reliable FPGA server solution used for executing encryption/decryption queries. The proposed server deploys bitstream relocation and modular redundancy to mitigate both permanent and transient faults in the device. It also deploys a novel Built-In Self- Test (BIST) diagnosis scheme, specifically designed to detect emerging permanent faults in the system at run-time. The second application is a data mining application where DPR is used to increase the computational density of a system used to implement the Frequent Itemset Mining (FIM) problem.

Recently, there has been growing interest in custom and reconfigurable hardware. However, commercial hardware platforms have limitations for research, because they are optimized for specific use-cases or have proprietary parts. To address this problem, the Systems Group at ETH built Enzian, a new computing platform tailored for research and for exploring novel hardware/software co-designs. However, there is a lack of existing use cases that could promote Enzian as a viable research platform. In addition, Enzian, like most CPU-FPGA hybrid systems, is hard to use for computer scientists without a hardware development background. In this thesis, we add OpenCL support to Enzian, which not only represents a real-world use case but also increases the usability of the platform. Using the flexibility of the Enzian computing platform, we explore different designs and compare their performance with existing systems. Our preliminary experimental results show that Enzian can support key features of existing OpenCL implementations. Because of OpenCL, we were able to port existing applications to Enzian with little effort. Hence, OpenCL improves the usability of Enzian and serves as a good use case to prove the feasibility of the platform. To summarize, Enzian proved to be a viable platform for computer systems research and will hopefully support researchers in developing innovative hardware solutions.

With the increased usage of optical wireless communication, finding appropriate parameters for reliable transmission and providing efficient channel performance have become of challenging interest in research and industry. This has been a strong motivation to examine and develop methods and techniques to find suitable link parameters to increase the channel availability. This thesis is mainly concerned with designing, implementing and adapting intelligent algorithms to solve for parameter selection, channel prediction, and channel adaptation in dynamic optical wireless channels. The problem could be solved with other methods such as binary and sequential search; however, intelligent systems have the ability to find optimal results with more reliability, time efficiency and increased flexibility. The research focuses on single and multi-objective selection techniques using application-specific genetic algorithm (ASGA) in the outdoors line-of-sight (LOS) optical wireless channel where parameters have different effects on the channel performance and may affect the behaviour of other channel parameters. The technique is well-established at pre-installation stages of the channel, and could be also applied at run-time if a reconfigurable hardware is installed. An intelligent system, which uses a genetic algorithm predicted and optimized optical wireless channel in the (LOS) field, is presented. The prediction technique is proposed to estimate the bit error rate (BER) at the receiver, and suggests appropriate selection of link parameters. In this research, the work is developed based on on-off keying (OOK) modulation, and makes use of different weather conditions for channel modeling. A first attempt is made with a GA-based selection for transmission wavelengths (700nm to 1600nm), the overall deterministic attenuations being estimated by a visibility model, where the changes in visibility decide about the wavelength control margin. The research is then extended to consider various external link parameters scaled by look-up tables that meet the optical wireless industry. It shows that the transmission power should not always be the only costin the channel, and there are other parameters worthy of control. Principal Component Analysis is applied targeting the ASGA selected datasets to extract the contribution of each parameter to the output, and the implicit relations that exist among data sets to achieve a certain bit-error-rate. An Artificial Neural Network (ANN) is then applied to the channel for BER prediction; this may also validate the pre-installation advice done by PCA. Finally, a two-stage modelling using a neuro-fuzzy hybrid algorithm used for adapting the channel by monitoring the link range and total attenuations in the channel. Through analysing the simulation results using these intelligent systems algorithms, the thesis aims at providing maximum utilization of channel parameters for achieving optimum channel performance and increased availability under the application of various intelligent systems, which demonstrate their efficiency and effectiveness as compared with other techniques.

The precision used in an algorithm affects the error and performance of individual computations, the memory usage, and the potential parallelism for a fixed hardware budget. However, when migrating an algorithm onto hardware, the potential improvements that can be obtained by tuning the precision throughout an algorithm to meet a range or error specification are often overlooked; the major reason is that it is hard to choose a number system which can guarantee any such specification can be met. Instead, the problem is mitigated by opting to use IEEE standard double precision arithmetic so as to be ‘no worse’ than a software implementation. However, the flexibility in the number representation is one of the key factors that can be exploited on reconfigurable hardware such as FPGAs, and hence ignoring this potential significantly limits the performance achievable. In order to optimise the performance of hardware reliably, we require a method that can tractably calculate tight bounds for the error or range of any variable within an algorithm, but currently only a handful of methods to calculate such bounds exist, and these either sacrifice tightness or tractability, whilst simulation-based methods cannot guarantee the given error estimate. This thesis presents a new method to calculate these bounds, taking into account both input ranges and finite precision effects, which we show to be, in general, tighter in comparison to existing methods; this in turn can be used to tune the hardware to the algorithm specifications. We demonstrate the use of this software to optimise hardware for various algorithms to accelerate the solution of a system of linear equations, which forms the basis of many problems in engineering and science, and show that significant performance gains can be obtained by using this new approach in conjunction with more traditional hardware optimisations.

Orthogonal frequency division multiplexing (OFDM) is a multicarrier modulation technique that has become a viable method for wireless communication systems due to the high spectral efficiency, immunity to multipath distortion, and being flexible to integrate with other techniques. However, the high-peak-to-average power ratio and sensitivity to synchronization errors are the major drawbacks for OFDM systems. The algorithms and architectures for symbol timing and frequency synchronization have been addressed in this thesis because of their critical requirements in the development and implementation of wireless OFDM systems. For the frequency synchronization, two efficient carrier frequency offset (CFO) estimation methods based on the power and phase difference measurements between the subcarriers in consecutive OFDM symbols have been presented and the power difference measurement technique is mapped onto reconfigurable hardware architecture. The performance of the considered CFO estimators is investigated in the presence of timing uncertainty conditions. The power difference measurements approach is further investigated for timing synchronization in OFDM systems with constant modulus constellation. A new symbol timing estimator has been proposed by measuring the power difference either between adjacent subcarriers or the same subcarrier in consecutive OFDM symbols. The proposed timing metric has been realized in feedforward and feedback configurations, and different implementation strategies have been considered to enhance the performance and reduce the complexity. Recently, multiple-input multiple-output (MIMO) wireless communication systems have received considerable attention. Therefore, the proposed algorithms have also been extended for timing recovery and frequency synchronization in MIMO-OFDM systems. Unlike other techniques, the proposed timing and frequency synchronization architectures are totally blind in the sense that they do not require any information about the transmitted data, the channel state or the signal-to-noise-ratio (SNR). The proposed frequency synchronization architecture has low complexity because it can be implemented efficiently using the three points parameter estimation approach. The simulation results confirmed that the proposed algorithms provide accurate estimates for the synchronization parameters using a short observation window. In addition, the proposed synchronization techniques have demonstrated robust performance over frequency selective fading channels that significantly outperform other well-established methods which will in turn benefit the overall OFDM system performance. Furthermore, an architectural exploration for mapping the proposed frequency synchronization algorithm, in particular the CFO estimation based on the power difference measurements, on reconfigurable computing architecture has been investigated. The proposed reconfigurable parallel and multiplexed-stream architectures with different implementation alternatives have been simulated, verified and compared for field programmable gate array (FPGA) implementation using the Xilinx’s DSP design flow.

This research undergone is an inter-disciplinary project with the Civil Engineering Department, which focuses on acceleration of the numerical solutions of Partial differential equations (PDEs) describing continuous solid bodies (e.g. a dam or an aircraft wing). Numerical techniques for solutions to PDEs are generally computationally demanding and data intensive. One approach to acceleration of their numerical solutions is to use FPGA based reconfigurable computing boards. The aim of this research is to investigate the features of various algorithms for the numerical solution of Laplace’s equation (the targeted PDE problem) in order to establish how well they can be mapped onto reconfigurable hardware accelerators. Finite difference methods and finite element methods are used to solve the PDE and they are characterized in terms of their operation count, sequential and parallel content, communication requirements and amenability to domain decomposition. These are then matched to abstract models of the capabilities of FPGA-based reconfigurable computing platforms. The performance of different algorithms is compared and discussed. The resulting hardware design will be suitable for platforms ranging from single board add-ins for general PCs to reconfigurable supercomputers such as the Cray XD1. However, the principal aim in this research has been to seek methods that perform well on low-cost platforms. In this thesis, several algorithms of solving the PDE are implemented on FPGA-based reconfigurable computing systems. Domain decomposition is used to take advantage of the embedded memory within the FPGA, which is used as a cache to store the data for the current sub-domain in order to eliminate communication and synchronization delays between the sub-domains and to support a very large number of parallel pipelines. Using Fourier decomposition, the 32bit floating-point hardware/software design can achieve a speed-up of 38 for 3-D 256x256x256 finite difference method on a single FPGA board (based on a Virtex2V6000 FPGA) compared to a software solution implemented in the same algorithm on a 2.4 GHz Pentium 4 PC which supports SSE2. The 32 bit floating-point hardware-software coprocessor for the 3D tetrahedral finite element problem with 48,000 elements using the preconditioned conjugate gradient method can achieve a speed-up of 40 for a single FPGA board (based on a Virtex4VLX160 FPGA) compared to a software solution.

Recently, the more widespread use of three-dimensional (3-D) imaging modalities, such as magnetic resonance imaging (MRI), computed tomography (CT), positron emission tomography (PET), and ultrasound (US) have generated a massive amount of volumetric data. These have provided an impetus to the development of other applications, in particular telemedicine and teleradiology. In these fields, medical image compression is important since both efficient storage and transmission of data through high-bandwidth digital communication lines are of crucial importance. Despite their advantages, most 3-D medical imaging algorithms are computationally intensive with matrix transformation as the most fundamental operation involved in the transform-based methods. Therefore, there is a real need for high-performance systems, whilst keeping architectures exible to allow for quick upgradeability with real-time applications. Moreover, in order to obtain efficient solutions for large medical volumes data, an efficient implementation of these operations is of significant importance. Reconfigurable hardware, in the form of field programmable gate arrays (FPGAs) has been proposed as viable system building block in the construction of high-performance systems at an economical price. Consequently, FPGAs seem an ideal candidate to harness and exploit their inherent advantages such as massive parallelism capabilities, multimillion gate counts, and special low-power packages. The key achievements of the work presented in this thesis are summarised as follows. Two architectures for 3-D Haar wavelet transform (HWT) have been proposed based on transpose-based computation and partial reconfiguration suitable for 3-D medical imaging applications. These applications require continuous hardware servicing, and as a result dynamic partial reconfiguration (DPR) has been introduced. Comparative study for both non-partial and partial reconfiguration implementation has shown that DPR offers many advantages and leads to a compelling solution for implementing computationally intensive applications such as 3-D medical image compression. Using DPR, several large systems are mapped to small hardware resources, and the area, power consumption as well as maximum frequency are optimised and improved. Moreover, an FPGA-based architecture of the finite Radon transform (FRAT)with three design strategies has been proposed: direct implementation of pseudo-code with a sequential or pipelined description, and block random access memory (BRAM)- based method. An analysis with various medical imaging modalities has been carried out. Results obtained for image de-noising implementation using FRAT exhibits promising results in reducing Gaussian white noise in medical images. In terms of hardware implementation, promising trade-offs on maximum frequency, throughput and area are also achieved. Furthermore, a novel hardware implementation of 3-D medical image compression system with context-based adaptive variable length coding (CAVLC) has been proposed. An evaluation of the 3-D integer transform (IT) and the discrete wavelet transform (DWT) with lifting scheme (LS) for transform blocks reveal that 3-D IT demonstrates better computational complexity than the 3-D DWT, whilst the 3-D DWT with LS exhibits a lossless compression that is significantly useful for medical image compression. Additionally, an architecture of CAVLC that is capable of compressing high-definition (HD) images in real-time without any buffer between the quantiser and the entropy coder is proposed. Through a judicious parallelisation, promising results have been obtained with limited resources. In summary, this research is tackling the issues of massive 3-D medical volumes data that requires compression as well as hardware implementation to accelerate the slowest operations in the system. Results obtained also reveal a significant achievement in terms of the architecture efficiency and applications performance.

This thesis is concerned with the optimisation of Digital Signal Processing (DSP) algorithm implementations on reconfigurable hardware via the selection of appropriate word-lengths for the signals in these algorithms, in order to minimise system power consumption. Whilst existing word-length optimisation work has concentrated on the minimisation of the area of algorithm implementations, this work introduces the rst set of power consumption models that can be evaluated quickly enough to be used within the search of the enormous design space of multiple word-length optimisation problems. These models achieve their speed by estimating both the power consumed within the arithmetic components of an algorithm and the power in the routing wires that connect these components, using only a high-level description of the algorithm itself. Trading o a small reduction in power model accuracy for a large increase in speed is one of the major contributions of this thesis. In addition to the work on power consumption modelling, this thesis also develops a new technique for selecting the appropriate word-lengths for an algorithm implementation in order to minimise its cost in terms of power (or some other metric for which models are available). The method developed is able to provide tight lower and upper bounds on the optimal cost that can be obtained for a particular word-length optimisation problem and can, as a result, nd provably near-optimal solutions to word-length optimisation problems without resorting to an NP-hard search of the design space. Finally the costs of systems optimised via the proposed technique are compared to those obtainable by word-length optimisation for minimisation of other metrics (such as logic area) and the results compared, providing greater insight into the nature of wordlength optimisation problems and the extent of the improvements obtainable by them.

Market requirements always influence the semiconductor industry. The coexistence of multiple standards, which exhibit distinct mobility and data rates, makes that a flexible convergence of current wireless standards and services is expected from beyond 3G systems. However, this trend needs a strong demand for underlying hardware architectures to achieve unprecedented performance, flexibility, low power consumption and time-to-market requirements. Since forward error correction algorithms demand the most computational cost of the whole physical layer system, this thesis employs two forward error correction cases, Viterbi decoder and double binary circular Turbo decoder, to investigate three potential reconfigurable hardware architectures for beyond 3G wireless communication system. Firstly, a domain specific reconfigurable Viterbi decoder fabric is introduced, which can support multiple Viterbi decoders with different constraint lengths and code rates. In addition, it also provides near ASIC performance in terms of power consumption and area. In order to further reduce the design and verification cost of this domain specific reconfigurable design, Chapter 4 presents another reconfigurable architecture which can be automatically generated and programmed by its associated CAD framework. Composed of heterogeneous coarse-grained processing units and a 2-D interconnection mesh, this reconfigurable architecture demonstrates significant power and area savings as compared with commercial FPGAs, RICA, reconfigurable instruction cell array, which is a dynamic reconfigurable architecture programmed by ANSI C, has been developed as a feasible solution for future wireless and multimedia applications. In Chapter 5, several advanced optimization approaches are proposed to efficiently implement the Viterbi decoder on RICA architecture. Furthermore, Chapter 6 and Chapter 7 demonstrate the implementation of a more complex application, double binary circular Turbo decoder. In Chapter 6, a system model is built to investigate the suitable decoding algorithm which can balance the decoding throughput and performance degradation. On the other hand, appropriate quantization scheme for the decoding implementation is devised based on a bit-true model. Finally, an optimized double binary circular Turbo decoder which can provide scalable decoding throughput is demonstrated on the RICA architecture.

Current approaches towards building a reconfigurable processor are targeted towards general purpose computing or a limited range of media specific applications and are not specifically tuned for mobile multimedia applications. The complexity, real-time constraints and cost efficient implementations of future multimedia systems need to be addressed early in the design lifecycle. Besides, the increasing demand for mobile multimedia processing with stringent performance constraints for reduced power, lower chip area and high flexibility naturally demand an architecture tailored specifically for low power image and video processing applications. The research undertaken and presented in this thes~s is targeted towards developing a powerefficient reconfigurable silicon core s~itable for integration within a System-on-aChip (SoC) design framework. A reusable cluster based approach was employed to identify specific sequences of operations that can be implemented and accelerated using reconfigurable hardware. A strong focus of this work is on image transformations and video processing which tends to dominate computational requirements involving up to two-thirds of computational complexity of a video or image encoder. A set of application benchmarks (discrete cosine transform, discrete wavelet transform and motion estimation) were used as case studies to demonstrate the computational efficiency and flexibility of the proposed domain-specific reconfigurable architecture (DSRA) presented in this thesis. These case studies were validated, evaluated and compared in . terms of their performance cost metrics namely speed, silicon area and dynamic power consumption. A key feature of the proposed architecture is its capability to cater to a range of existing benchmark architectures by reconfiguring them to suit a broad range of specifications. This work demonstrates and quantifies that a domainspecific reconfigurable approach provides a middle-ground between standard cell ASIC design and SRAM programmable FPGA implementation.

Neuromorphic computers take inspiration from the brain to perform computation in a way similar to how a brain works. They perform computation by evaluating Spiking Neural Networks (SNN) to model how the electronic pulses travel through a collection of neurons. The neurons in the network spike, or fire a pulse, once the accumulated inputs to the neuron exceed a specific threshold. Field-Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), and other chip/multi-chip level implementations can be used to construct Dynamic Adaptive Neural Network Arrays (DANNA) and its successor DANNA2. In many use cases, the neuromorphic hardware is connected to a traditional computing system that is used to load neural network configurations, provide network input, process network output, and monitor the status of the network. To ensure robust communication, a custom, hardware-based, go-back-n, automatic repeat request protocol is presented, which allows for high-throughput, low-latency, error-free communication using the Aurora link-level protocol over the GTX/GTH high-speed serial transceivers found on Xilinx FPGAs. Multiple DANNA2 element cores are tiled into a grid array and placed within a KCU1500 Kintex Ultrascale FPGA to build a reconfigurable hardware neuromorphic processor. For resource-constrained environments, these element cores can also be densely packed onto the FPGA for a specific network, requiring fewer resources for a non-reconfigurable neuromorphic processor. For high-performance computation, multiple reconfigurable neuromorphic processors with grid arrays are tiled together with a Neuromorphic Array Communication Controller (NACC) to build a large-scale neuromorphic system called Scaled-up NACC (SNACC). SNACC uses scalable, high-performance, point-to-point connections to network the neuromorphic processors into a two-dimensional array. The neuromorphic processors are connected back to the host PC through a hierarchical, high-speed network made possible through the use of one or more NACCs. These new hardware DANNA2 neuromorphic processors are used to further research with recurrent spiking neural networks (RSNNs). Specifically, this work uses the new hardware for evolutionary optimization of neural networks using genetic algorithms, for reservoir computing, and for solving graph algorithms. Additionally, the hardware can be used for real-time processing as demonstrated with target acquisition and obstacle avoidance on a ground-roaming autonomous robot.

New communication standards and the requirements of modern mobile-device’s users push silicon towards processing more data in an increasingly shorter time; this is accurately the case for new compression formats targeting high-quality low-bandwidth multimedia. This presses forward the need for new programmable hardware solutions that intrinsically achieves generality, high-performance and, most importantly, low power consumption. This work investigates the design of reconfigurable hardware architectures to address these issues. Two novel solutions are thus proposed along with the implementation of several multimedia applications on them; the first architecture fits as a middle ground between FPGAs and ASICs in terms for performance and costs. This is achieved by using coarse-grain functional units combined with programmable interconnects to build flexible, high-performance and low-power circuits. A framework for generating and programming the custom domain-specific reconfigurable arrays is also proposed. The tool-flow leverages some of the design effort that goes in creating and using the arrays by facilitating the reuse of previous design elements. Furthermore, this work proposes novel direction-aware routing elements to allow efficient tailoring of interconnects structures to the application. The second proposed processing architecture adds the dimension of high-level programmability to the reconfigurable arrays. This is achieved by using functional units that can be directly matched to elements in a complier’s internal representation of software. By using a custom instruction-controller the array can execute control operations in a similar way to processors, while at the same time allowing highly efficient mapping of datapath circuits. Coupled to the low-power and high-throughput achieved, this creates a viable alternative to FPGAs, DSPs and ASICs suitable for deployment in high performance mobile applications.

This thesis addresses the use of reconfigurable hardware in computing platforms, in order to harness the performance benefits of dedicated hardware whilst maintaining the flexibility associated with software. Although the reconfigurable computing concept is not new, the low level nature of the supporting tools normally used, together with the consequent limited level of abstraction and resultant lack of backwards compatibility, has prevented the widespread adoption of this technology. In addition, bandwidth and architectural limitations, have seriously constrained the potential improvements in performance. A review of existing approaches and tools flows is conducted to highlight the current problems being faced in this field. The objective of the work presented in this thesis is to introduce a radically new approach to reconfigurable computing tool flows. The runtime based tool flow introduces complete abstraction between the application developer and the underlying hardware. This new technique eliminates the ease of use and backwards compatibility issues that have plagued the reconfigurable computing concept, and could pave the way for viable mainstream reconfigurable computing platforms. An easy to use, cycle accurate behavioural modelling system is also presented, which was used extensively during the early exploration of new concepts and architectures. Some performance improvements produced by the new reconfigurable computing tool flow, when applied to both a MIPS based embedded platform, and the Cray XDl, are also presented. These results are then analyzed and the hardware and software factors affecting the performance increases that were obtained are discussed, together with potential techniques that could be used to further increase the performance of the system. Lastly a heterogenous computing concept is proposed, in which, a computer system, containing multiple types of computational resource is envisaged, each having their own strengths and weaknesses (e.g. DSPs, CPUs, FPGAs). A revolutionary new method of fully exploiting the potential of such a system, whilst maintaining scalability, backwards compatibility, and ease of use is also presented.

Hardware security threats have become a major issue in the technology sector and cyberspace. In 2011, more than 1300 counterfeit incidents were reported from around the world to the Electronic Resellers Association International (ERAI). The incidents reported in 2011 were more than double compared to the incidents reported in 2010 and 2008. The federal contract report states that counterfeiting of electronic parts has threatened the operability and reliability of the US weapons system. Electronic parts counterfeiting has become a very big business perpetrated by corrupt operators. Just like ASIC semiconductors, reconfigurable hardware is also prone to hardware security threats. The most commonly used reconfigurable hardware is the Field Programmable Gate Array (FPGA). Demand for FPGAs has increased as can be seen by the growth in FPGA companies such as Xilinx and Altera. Despite the increased demand and use of FPGAs in the market, there is a great concern that security is not currently a part of the FPGA hardware and software to the fullest extent. Design theft, and hardware tampering threats on FPGAs can be dealt using Ring Oscillator Physical Unclonable Function (ROPUF). A ROPUF takes advantage of the process variation on a silicon chip to generate a unique ID for the purpose of authentication. A ROPUF can be implemented on an FPGA chip to produce a unique ID for each FPGA chip. An adversary that tries to tamper with the ROPUF inadvertently changes the properties of the process variation in the silicon chip; thus any tampering attempt can be detected. In this research, ROPUF based hardware security for FPGAs is presented. A total of 50 Xilinx FPGAs are used in our investigation. Performance in terms of uniqueness and reliability is evaluated. The effects of temperature variation, voltage variation, and aging on these parameters are also studied. Our work shows that lower number of stages used in the Ring Oscillator (RO) offers better security feature. The lower number of stages used in ROs yield higher Challenge and Response Pairs (CRPs). The higher number of CRPs contributes to higher security. In addition, we have introduced a technique called Random Patch Mixer (RPM) to minimize the systematic variations effect on the frequency generated from ROPUFs on FPGA. The results obtained by using RPM technique are shown to be better than other techniques that have been proposed before. The responses generated from ROPUF after applying the RPM technique passed most of the NIST statistical test for randomness. Finally, we show how the ROPUF can be used for the security of a Smart Grid. The security of ROPUF system is also tested using support vector machine (SVM). The SVM is trained using a large data set of challenges to predict the response sets. Results obtained show that the SVM fails to predict ROPUF responses based on the challenges, thus enhancing the security offered by the proposed authentication system.

The usefulness of reconfigurable hardware has been shown in research and commercial applications. Unquestionably, this has and will lead to, unique avenues of thought within computer science being explored. The interest by researchers in some specific areas has led to manufacturers developing devices which were enhanced in their ability to dynamically be configured within a run-time context. These improvements are on-going and rapid progress is being made, producing high density, system-on-a-chip capable devices, with fast run-time reconfiguration. The advancements in this technology have particularly led to a convergence between software and hardware domains, in the sense that algorithms can be implemented in either; the choice being dependent only in terms of efficiency within the medium itself. Older methods for development with these devices have become rapidly dated and inflexible. Very few suitable tools exist, for example, which are capable of fully utilising the inherent capabilities of such hardware. The approach taken here allows the division between hardware and software to be diminished. Component designs, which may be hardware description language (HDL) based or synthesised algorithms, become easily manipulated and interacted with through a run-time engine, that can deploy elements at will to local or distributed devices. Such entities are essentially hybrid in nature, possessing both hardware and software functionality. These processes are sufficiently self-supporting, to be capable of being used outside of the run-time system within a normal Java development environment. This work explores how hardware entities can become as dynamic as memory based algorithms within conventional von Neumann based systems, providing the means for extending the software programming paradigm into such areas. It analyses the possibilities of applying object-oriented and occam/Communicating Sequential Processes (CSP) based concurrency philosophies to these highly mobile, hardware processes.

Continuing increases in both the size and complexity of digital signal processing (DSP) systems places a considerable demand on the design engineer to develop hardware architectures capable of fulfilling the growing functional requirements expected of modern DSP devices. Automated circuit design techniques provide the design engineer with a tool to more effectively generate high performance signal processors capable of meeting demanding specifications. Evolvable hardware (EHW) is a relatively new approach to automated circuit design which utilises advances in reconfigurable hardware technology and the power of modern micro pro­cessors to generate circuits based on the principles of natural selection and evolution. This thesis investigates the suitability of software-biased and hardware oriented programmable platforms, configured via EHW, and tailored for the automated design of high performance DSP circuits. Performance criteria such as timing, area and circuit robustness are considered. A number of benchmarked DSP circuits were initially considered. It was shown that by using larger functional logic macros as building blocks EHW is more successful at generating circuit solutions than if only gate primitives are used. In addition, the circuits generated are of comparable or better performance than equivalent circuits developed using a standard digital design methodology. Results also indicated that for more complex DSP functions to be generated, EHW platforms must use larger functional blocks, constrained for a specific application. Finite Impulse Response (FIR) filters were identified as the backbone of many DSP applica­tions, and the multiplication unit was targeted as the performance critical component. A novel Programmable Arithmetic Logic Unit (PALU) was therefore developed as a functional building block suitable for automated digital filter design using EHW. The PALU replaces coefficient multiplication with a series of bit-shifts, additions and subtractions. Two distinct arrays of PALU were developed based on conventional FPGA and PLA re-configurable hardware architectures. Results show that a PLA architecture with 2 levels of hierarchical interconnect and column-based fixed tap outputs provides a platform most suited to automated filter design using the EHW technique. The PLA was also shown to be robust to faults covering up to 25% of the array when configured using EHW.

Evolvable Hardware (EHW), as an alternative method for logic design, became more attractive recently, because of its algebra-independent techniques for generating selfadaptive self-reconfigurable hardware. This thesis investigates and relates both evaluation and evolutionary processes, emphasizing the need to address problems arising from data complexity. Evaluation processes, capable of evolving cost-optimised fully functional circuits are investigated. The need for an extrinsic EHW approach (software models) independent of the concerns of any implementation technologies is emphasized. It is also shown how the function description may be adapted for use in the EHW approach. A number of issues of evaluation process are addressed: these include choice of optimisation criteria, multi-objective optimisation tedmiques in EHW and probabilistic analysis of evolutionary processes. The concept of self-adaptive extrinsic EHW method is developed. This approach emphasizes the circuit layout evolution together with circuit functionality. A chromosome representation for such system is introduced, and a number of genetic operators and evolutionary algorithms in support of this approach are presented. The genetic operators change the genetic material at the different levels of chromosome representation. Furthermore, a chromosome representation is adapted to the function-level EHW approach. As a result, the modularised systems are evolved using multi-output building blocks. This chromosome representation overcomes the problem of long string chromosome. Together, these techniques facilitate the construction of systems to evolve logic functions of large number of variables. A method for achieving this using bidirectional incremental evolution is documented. It is demonstrated that the integration of a dynamic evaluation process and self-adaptive function-level EHW approach allows the bidirectional incremental evolution to successfully evolve more complex systems than traditionally evolved before. Thereby it provides a firm foundation for the evolution of complex systems. Finally, the universality of these techniques is proved by applying them to multivalued combinational logic design. Empirical study of this application shows that there is no fundamental difference in approach for both binary and multi-valued logic design problems.

In recent years, network bandwidth has increased at a rapid pace, moving from 10G, to 40G/100G, to 400G. CPU frequency on the other hand has been stagnant. As a result, more and more CPU cycles have to be allocated to network processing to keep up with the increasing network bandwidth. At the same time, we have seen exponential growth in data requiring distributed systems to process it. While these systems benefit from the increased network bandwidth, their ability to scale out is limited by inefficiencies in I/O and data movement. Under the premise that most of such computation is distributed, one question remains as to whether data processing operations can be offloaded to the network. In this thesis, we explore two approaches to enable in-network data processing and thereby reduce burden on the CPU. Our first approach places data processing accelerators, such as FPGAs, in the network. To enable network-attached accelerators, we introduce a scalable network stack architecture for FPGAs supporting thousands of concurrent connections, a requirement of data center applications. Based on this architecture, we implement a TCP/IP stack that allows the seamless integration of accelerators into the existing network infrastructure. In our second approach, we enable data processing operations in the network by enhancing the functionality of the network card. In particular, we present Smart Remote Memory (STROM), which extends Remote Direct Memory Access (RDMA) with the capability to deploy acceleration kernels on the network card. These acceleration kernels can, for instance, directly access the remote host memory to traverse remote data structures such as lists or indexes. In addition to that, they can execute stream-based operations, e.g., filtering or aggregation, on data that is passing through the network card to the host memory, or vice versa. As part of this thesis, we implemented and released an open source TCP/IP stack for reconfigurable hardware. The stack enables network-attached accelerators and has been deployed successfully in a number of research and commercial systems. Following on from this success, we released an open source FPGA-based RDMA NIC, which we used as a prototyping platform for STROM, to facilitate more research in this area.

With the rapid migration of physical layer design of radio towards software, it becomes necessary to select or develop the platform and tools that help in achieving rapid design and development along with flexibility and reconfigurability. The availability of field programmable gate arrays (FPGAs) has promoted the concept of reconfigurable hardware for software defined radio (SDR). It enables the designer to create high speed radios with flexibility, low latency and high throughput. Generally, the traditional method of designing FPGA based radios limits productivity. Productivity can be improved using Model based design (MBD) tools. These tools encourage a modular way of developing waveforms for radios. The tools based on MBD have been the focus of recent research exploring the concept of the platform independent model (PIM) and portability across platforms by the platform specific model (PSM). The thesis presented here explores the tools based on MBD to achieve prototyping for wireless standards like IEEE 802.11a and IEEE 802.16e on reconfigurable hardware. It also describes the interfacing of the universal software radio peripheral (USRP2), acting as a radio frequency (RF) front end, with an additional FPGA board for baseband processing.

Video coding is widely used in our daily life. Due to its high computational complexity, hardware implementation is usually preferred. In this research, we investigate both ASIC hardware design approach and reconfigurable hardware design approach for video coding applications. First, we present a unified architecture that can perform Discrete Cosine Transform (DCT), Inverse Discrete Cosine Transform (IDCT), DCT domain motion estimation and compensation (DCT-ME/MC). Our proposed architecture is a Wavefront Array-based Processor with a highly modular structure consisting of 8*8 Processing Elements (PEs). By utilizing statistical properties and arithmetic operations, it can be used as a high performance hardware accelerator for video transcoding applications. We show how different core algorithms can be mapped onto the same hardware fabric and can be executed through the pre-defined PEs. In addition to the simplified design process of the proposed architecture and savings of the hardware resources, we also demonstrate that high throughput rate can be achieved for IDCT and DCT-MC by fully utilizing the sparseness property of DCT coefficient matrix. Compared to fixed hardware architecture using ASIC design approach, reconfigurable hardware design approach has higher flexibility, lower cost, and faster time-to-market. We propose a self-reconfigurable platform which can reconfigure the architecture of DCT computations during run-time using dynamic partial reconfiguration. The scalable architecture for DCT computations can compute different number of DCT coefficients in the zig-zag scan order to adapt to different requirements, such as power consumption, hardware resource, and performance. We propose a configuration manager which is implemented in the embedded processor in order to adaptively control the reconfiguration of scalable DCT architecture during run-time. In addition, we use LZSS algorithm for compression of the partial bitstreams and on-chip BlockRAM as a cache to reduce latency overhead for loading the partial bitstreams from the off-chip memory for run-time reconfiguration. A hardware module is designed for parallel reconfiguration of the partial bitstreams. The experimental results show that our approach can reduce the external memory accesses by 69% and can achieve 400 MBytes/s reconfiguration rate. Detailed trade-offs of power, throughput, and quality are investigated, and used as a criterion for self-reconfiguration. Prediction algorithm of zero quantized DCT (ZQDCT) to control the run-time reconfiguration of the proposed scalable architecture has been used, and 12 different modes of DCT computations including zonal coding, multi-block processing, and parallel-sequential stage modes are supported to reduce power consumptions, required hardware resources, and computation time with a small quality degradation. Detailed trade-offs of power, throughput, and quality are investigated, and used as a criterion for self-reconfiguration to meet the requirements set by the users.

Adaptive computing systems have proven useful for implementing a wide range of algorithms. A limitation of current systems is the relatively small amount of reconfigurable hardware resources. Many algorithms require more hardware resources than are available. One solution to this problem is runtime reconfiguration (RTR). Using RTR techniques, a large algorithm is implemented as a collection of configurations for the reconfigurable hardware. These configurations are loaded onto the reconfigurable hardware as necessary to implement the algorithm. A primary limitation of RTR is that the reconfiguration process is slow. Therefore, methods of decreasing reconfiguration time are desirable. Another method of implementing large algorithms on small hardware is to use multiple configurable computing platforms connected via a communication network. RTR techniques can be used in conjunction with this method to further increase hardware availability. In this case reconfiguration time is increased by the overhead of transmitting data across the communication network. Methods of decreasing network overhead are desirable. This thesis discusses the use of caching techniques to decrease reconfiguration time. An architecture for caching configurations is implemented on a configurable computing system platform. The use of caching to decrease network overhead is discussed and exhibited. An example application is implemented and used to evaluate the effects of caching on reconfiguration time and algorithm performance.

The security of a radio system hinges on its ability to effectively authenticate a user. This work proposes a two-factor authentication scheme using a token and a biometric. The users' access rights are determined during authentication and the users are served only those channels of data that they are privileged to receive. The strengths and the weaknesses of the implementation in reconfigurable hardware are identified. The capabilities of the scheme are put into perspective by comparing it to a high-end authentication system and by evaluating the use of standardized APIs and low-end authentication devices. Modifications to the system are suggested to improve the level of security the scheme provides. Finally, a baseline study is carried out to measure the data processing performance of a radio developed in reconfigurable hardware, which uses the proposed authentication scheme.

Software radios have evolved as multimode, programmable digital radios that perform radio functions using digital signal processing algorithms. They have been designed as software programmable radios using a combination of various hardware elements and structures. In this dissertation a {em{soft radio}} refers to a completely configurable radio that can be programmed through software, to change the radio behavior including the hardware functionality. Conventional software radios achieve flexibility through software with the use of static hardware. While these radios have the flexibility to operate in multiple modes, the hardware is not used efficiently. This inefficient utilization of hardware frequently limits the flexibility of software radios and the number of modes the radio can support. Soft radios however, attempt to gain flexibility through the use of reconfigurable hardware. The same piece of hardware can be configured to perform different functions based on the mode the radio is operating in. While many soft/software radio architectures have been suggested and implemented, there remains a lack of a formal design methodology that can be used to design and implement reconfigurable soft radios. Most designs are based on ad hoc approaches which are appropriate only for the problem at hand. After examining the design issues of a soft radio an architecture, called the {em{Layered Radio Architecture}}, is developed with the use of stream based processing and run-time reconfigurable hardware. These choices aid in maximizing performance with minimum hardware while keeping the architecture robust, simple, and scalable. The reconfigurable platform enables {em hardware paging} through reusability hardware. The stream-based approach gives a uniform modular structure to the processing modules and defines the protocol for interaction between various modules. The architecture describes a formal yet open design methodology and makes it possible to incorporate all of the features of a software radio while minimizing complexity issues. The layered architecture also defines the methodology for incorporating changes and updates into the system. The layered radio architecture assumes run-time reconfigurability of the hardware. This feature is not supported by existing commercial reconfigurable hardware, like FPGAs. An Custom Computing Machine (CCM), called Stallion that supports fast run time reconfiguration, has been developed at Virginia Tech. This dissertation describes the deficiencies of existing commercial reconfigurable hardware and shows how the Stallion is capable of supporting the layered radio architecture. The dissertation presents algorithms and procedures that can be used to implement the layered radio architecture using existing hardware. The architecture is validated with the implementation of two receivers: A single user CDMA receiver based on complex adaptive filtering and a W-CDMA downlink rake receiver with channel estimation. Performance analysis of these receivers show that it is important to keep the paging ratio high while maximizing utilization of the processing elements. The layered radio architecture with the use of Stallion can support existing high data rate systems.

As modern Data Center workloads become increasingly complex, constrained, and critical, mainstream CPU-centric computing has had ever more difficulty in keeping pace. Future data centers are moving towards a more fluid and heterogeneous model, with computation and communication no longer localized to commodity CPUs and routers. Next generation data-centric Data Centers will compute everywhere, whether data is stationary (e.g. in memory) or on the move (e.g. in network). While deploying FPGAs in NICS, as co-processors, in the router, and in Bump-in-the-Wire configurations is a step towards implementing the data-centric model, it is only part of the overall solution. The other part is actually leveraging this reconfigurable hardware. For this to happen, two problems must be addressed: code generation and deployment generation. By code generation we mean transforming abstract representations of an algorithm into equivalent hardware. Deployment generation refers to the runtime support needed to facilitate the execution of this hardware on an FPGA. Efforts at creating supporting tools in these two areas have thus far provided limited benefits. This is because the efforts are limited in one or more of the following ways: They i) do not provide fundamental solutions to a number of challenges, which makes them useful only to a limited group of (mostly) hardware developers, ii) are constrained in their scope, or iii) are ad hoc, i.e., specific to a single usage context, FPGA vendor, or Data Center configuration. Moreover, efforts in these areas have largely been mutually exclusive, which results in incompatibility across development layers; this requires wrappers to be designed to make interfaces compatible. As a result there is significant complexity and effort required to code and deploy efficient custom hardware for FPGAs; effort that may be orders-of-magnitude greater than for analogous software environments. The goal of this dissertation is to create a framework that enables reconfigurable logic in Data Centers to be targeted with the same level of effort as for a single CPU core. The underlying mechanism to this is a framework, which we refer to as Hardware as a Reconfigurable, Elastic and Specialized Service, or HaaRNESS. In this dissertation, we address two of the core challenges of HaaRNESS: reducing the complexity of code generation by constraining High Level Synthesis (HLS) toolflows, and replacing ad hoc models of deployment generation by generalizing and formalizing what is needed for a hardware Operating System. These parts are unified by the back-end of HLS toolflows which link generated compute pipelines with the operating system, and provide appropriate APIs, wrappers, and software runtimes. The contributions of this dissertation are the following: i) an empirically guided set of systematic transformations for generating high quality HLS code; ii) a framework for instrumenting HLS compiler to identify and remove optimization blockers; iii) a framework for RTL simulation and IP generation of HLS kernels for rapid turnaround; and iv) a framework for generalization and formalization of hardware operating systems to address the {\it ad hoc}'ness of existing deployment generation and ensure uniform structure and APIs.

According to the Electronic Resellers Association International (ERAI), counterfeit incidents have been increasing progressively since 2008. Reconfigurable hardware like Field Programmable Gate Array (FPGA), as well as ASIC semiconductors, are prone to security vulnerabilities due to their increased outsourcing and widespread implementations; both being extensively used in covert military and competitive commercial applications. Hence, hardware tampering threats and design piracy pose a significant threat on FPGAs because of their far-reaching employments. Ring Oscillator Physical Unclonable Function (ROPUF) has demonstrated potential in solving substantial safety concerns due to its capacity to generate random, yet chip-unique keys, capitalizing on the process variation while withstanding cloning and external attacks. Process manufacturing variation is uncontrollable and even with the uniformity of the chip manufacturing process, manufacturing variations exist. The ROPUF structure, although promising for FPGA-based platforms, is not area efficient in terms of response bit per RO circuit implementation. In this research work, a four input Stage-Configurable ROPUF (SCROPUF) based on XOR gates and a functional block which significantly increases the output frequency comparison pairs are designed. Subsequently, implementation of the area efficient SCROPUF design and quality factors evaluation in terms of uniqueness, bit aliasing, uniformity parameters and the NIST Statistical Tests for Randomness is performed on six Xilinx Artix-7 FPGAs. The purpose of the extensible SCROPUF design, along with the functional logic block incorporated in the model is to ensure dynamic operation with all of the 16 input combinations. This makes the transformation from one through five stages feasible in a single design. The proposed design also introduces significant dynamic attributes in terms of varying average frequencies with change in the input configurations of the PUF model. With the novel selectivity features, a designer can choose the most suitable configuration for specific applications. Apart from generating high challenge and response pairs (CRPs) compared to the other designs, experimental analysis with SCROPUF shows that it has a high average static intra-chip variation to the dynamic component ratio suggesting high uniqueness and good reliability (reproducibility) due to low bit-flip probability. The Random Patch Mixer (RPM) technique implemented in this work to offset the systematic variation effect in the response bit-stream is corroborated by the successful NIST statistical tests, therefore making the design suitable for cryptographic and authentication purposes.