21 results on '"Yao-Jen Lee"'
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2. Tri-Gate Ferroelectric FET Characterization and Modelling for Online Training of Neural Networks at Room Temperature and 233K.
3. Exploring the impacts of long-period corrugation and phase gratings on a cascade of phase-shifted lithium niobate waveguides with the combined theoretical and experimental approaches.
4. Low-temperature microwave annealing processes for future IC fabrication.
5. Dopant activation by microwave anneal.
6. Trapping/detrapping characteristics of electrons and holes under dynamic NBTI stress on HfO2 and HfSiON gate dielectrics.
7. 3D 65nm CMOS with 320°C microwave dopant activation.
8. A comprehensive study of Ge1−xSix on Ge for the Ge nMOSFETs with tensile stress, shallow junctions and reduced leakage.
9. Trapping and de-trapping characteristics in PBTI and dynamic PBTI between HfO2 and HfSiON gate dielectrics.
10. Local Strained Channel (LSC) nMOSFETs by Different Poly-Si Gate and SiN Capping Layer Thicknesses: Mobility Enhancement, Size Dependence, and Hot Carrier Stress.
11. High-performance Ni/SiO2/Si programmable metallization cell.
12. Microwave annealing effect on the resistivity of doped hydrogenated amorphous silicon on glass.
13. Comparison between the silicon microrings fabricated by Gaussian and variable shape electron beam lithography.
14. A novel three-terminal transistor-based Mach-Zehnder interferometric modulator on silicon-on-silicon (SOS) substrate.
15. Comparisons on performance improvement by nitride capping layer among different channel directions nMOSFETs.
16. Impacts of precursor flow rate and temperature of PECVD-SiN capping films on strained-channel NMOSFETs.
17. Impacts of a buffer layer and hi-wafers on the performance of strained-channel NMOSFETs with SiN capping layer.
18. Reliability of strained-channel NMOSFETs with SiN capping layer on hi-wafers with a thin LPCVD-TEOS buffer layer.
19. Spatially resolving the degradation of SPC thin-film transistors under AC stress.
20. Improved Hot Carrier Reliability in Strained-Channel NMOSFETS with TEOS Buffer Layer.
21. A novel bottom-up Ag contact (30nm diameter and 6.5 aspect ratio) technology by electroplating for 1Xnm and beyond technology.
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