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A fully-depleted SOI CMOS technology, being implemented in ITE, Warsaw, has been briefly described. Extensive wafer-scale electrical measurements have been done towards investigation of the technology stability. The measurements have been followed by I–V characteristics processing based on compact models of MOS transistors. The calculated electrophysical MOSFET parameters have been mapped and their distributions have been determined. The MOSFET parameter extraction has been supplied with additional measurements of the poly-Si resistors. Correlations between determined parameters have been also investigated. [ABSTRACT FROM PUBLISHER]

Characterization of gate-less nanowire (NW) sensor devices by means of test devices of similar geometry, equipped with metal gate electrode, has been proposed in the paper. Details of NW n-FET technology and microscope verification are presented. IDS(VGS) and IDS(VDS) DC characteristics have been measured and discussed in relation to a channel implanted phosphorus dose. 2-fin, 8-fin and 32-fin FETs have been compared using a normalization to the single fin device. A spread of NW devices characteristics and an influence of positive or negative incrementation of the voltage have been investigated. Conclusions related to sensor development have been drawn. [ABSTRACT FROM PUBLISHER]

NoC (Network-on-Chip) has been proposed as a new solution to deal with the global communication problem of complex SoC(System-on-Chip). An evaluation tool is essential for optimizing the NoC design, through which the functionality and performance of the NoC are verified. This paper presents a coverage-driven and hierarchical NoC verification platform based on System Verilog language. It is applicable to various NoCs with arbitrary size, topology, multiple interface protocols and various test structure. To verify the effectiveness of this platform, Mesh and Totus topology and the corresponding XY or TXY routing algorithms were adopted and applied to random uniform and random hot distribution simultaneously. Furthermore, the platform is also applied for evaluating different test schemes. The results of performance and test structure evaluation show that the verification platform improves the verification efficiency and has good adaptability and scalability as well. [ABSTRACT FROM PUBLISHER]