100 results on '"Stojanovic, V."'
Search Results
2. An Error-free 1 Tbps WDM Optical I/O Chiplet and Multi-wavelength Multi-port Laser
3. EP650 Ultrasound screening for endometrial abnormalities in patients on tamoxifen
4. Fully Integrated Coherent LiDAR in 3D-Integrated Silicon Photonics/65nm CMOS
5. Demonstration of 50-mV Digital Integrated Circuits with Microelectromechanical Relays
6. Monolithic integration of O-band photonic transceivers in a “zero-change” 32nm SOI CMOS
7. High-density 3D electronic-photonic integration
8. Circuits evening panel discussion 1: Is university circuit design research and education keeping up with industry needs?
9. A monolithically-integrated chip-to-chip optical link in bulk CMOS
10. A monolithically-integrated optical transmitter and receiver in a zero-change 45nm SOI process
11. Development of fast neutral etching for integrated circuits and nanotechnologies fast neutrals in gas
12. Comparison of Advanced and Standard Real-Time 3D Rendering Methods for Interactive Landscapes (Short Paper Version)
13. Photonic integration in a commercial scaled bulk-CMOS process
14. Designing Energy-Efficient Low-Diameter On-Chip Networks with Equalized Interconnects
15. Low-Complexity Pattern-Eliminating Codes for ISI-Limited Channels
16. Statistical Simulator for Block Coded Channels with Long Residual Interference
17. Practical Limits of Multi-Tone Signaling Over High-Speed Backplane Electrical Links
18. A 24Gb/s Software Programmable Multi-Channel Transmitter
19. A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors
20. High-speed serial links: design trends and challenges
21. Injection-locked clock receiver for monolithic optical link in 45nm SOI.
22. Design and demonstration of micro-electro-mechanical relay multipliers.
23. Addressing link-level design tradeoffs for integrated photonic interconnects.
24. A monolithically-integrated optical receiver in standard 45-nm SOI.
25. Digital link pre-emphasis with dynamic driver impedance modulation.
26. A low-power area-efficient switching scheme for charge-sharing DACs in SAR ADCs.
27. A signal-agnostic compressed sensing acquisition system for wireless and implantable sensors.
28. Analysis and demonstration of MEM-relay power gating.
29. Discrete-time, cyclostationary phase-locked loop model for jitter analysis.
30. Silicon-photonic clos networks for global on-chip communication.
31. An oscilloscope array for high-impedance device characterization.
32. Integrated circuit design with NEM relays.
33. Optimization-based framework for simultaneous circuit-and-system design-space exploration: A high-speed link example.
34. Cross sections and transport properties of negative bromine ions in Kr and Xe.
35. Electron and positron swarms: Collision and transport data and kinetic phenomena.
36. Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics.
37. A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR.
38. Power-centric design of high-speed I/Os.
39. SPC03-5: Analog Multi-Tone Signaling for High-Speed Backplane Electrical Links.
40. A 1-10 Gbps PAM2, PAM4, PAM2 partial response receiver analog front end with dynamic sampler swapping capability for backplane serial communications.
41. Modeling, simulation, and design of a multi-mode 2-10 Gb/sec fully adaptive serial link system.
42. Common-mode backchannel signaling system for differential high-speed links.
43. Adaptive equalization and data recovery in a dual-mode (PAM2/4) serial link transceiver.
44. Circuits and techniques for high-resolution measurement of on-chip power supply noise.
45. Modeling and analysis of high-speed links.
46. Methods for true power minimization.
47. Energy–delay tradeoffs in combinational logic using gate sizing and supply voltage optimization.
48. Complex geophysical investigations at the "Verige" bridge site location
49. Comparative analysis of latches and flip-flops for high-performance systems.
50. Energy-efficient active photonics in a zero-change, state-of-the-art CMOS process.
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.