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Your search keyword '"Sekhar, Vasarla Nagendra"' showing total 19 results
Start Over Author "Sekhar, Vasarla Nagendra" Publication Type Conference Materials
19 results on '"Sekhar, Vasarla Nagendra"'

18. Design, Assembly and Reliability of Large Die (21 x 21mm2) and Fine-pitch (150pm) Cu/Low-K Flip Chip Package

Author

Ong, Yue Ying, primary, Vaidyanathan, Kripesh, additional, Ho, Soon Wee, additional, Sekhar, Vasarla Nagendra, additional, Jong, Ming Ching, additional, Wai, Leong Ching, additional, Rao, Vempati Srinivasa, additional, Sheng, Vincent Lee Wen, additional, Ong, Jimmy, additional, Ong, Xuefen, additional, Zhang, Xiaowu, additional, Seung, Yoon Uk, additional, Lau, John, additional, Lim, Yeow Kheng, additional, Yeo, David, additional, Chan, Kai Chong, additional, Yanfeng, Zhang, additional, Tan, Juan Boon, additional, and Sohn, Dong Kyun, additional

Published
2008
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19. Challenges and approaches of TSV thin die stacking on organic substrate.

Author

Lim Pei-Siang, Sharon, Che Faxing, Chong Ser Choong, Chew Bi Rong, Michelle, Sekhar, Vasarla Nagendra, Rao, Vempati Srinivasa, and Chai Tai Chong

Abstract

The requirements for high density packaging such as smaller form factor, high performance and multi functionality electronics products have resulted in electronics industry moving towards 3D System in package technology (3D SIP). Some of the main advantages of 3D SIP packaging are high volume applications, smaller form factor, better connectivity between components in a 3D package, lower noise, lower power consumption and higher operating frequencies [1]. A 3D package is a cost effective solution as it helps to save placement and routing area on board using several IC process in the same module. A stacked die SiP package offers flexibility in combining die from different fab processes into a single package. Board area savings are realized by stacking the die vertically vs a side by side approach. This package technology is mainly used where X-Y size constraint is the critical requirement. Some of the key technologies needed to enable chip stacking include silicon through-vias and high-density lead-free interconnects [2]. In the paper, 2 different reflow approaches are used for the 3 die stacked flip chip assembly (i) sequential reflow and (ii) 3 die stacked simultaneous reflow. The effect of the reflow approaches of the stacked die assembly with TSV on die warpage, solder wetting, solder voids and bonding alignment is addressed in this paper. In addition, a simple D.O.E was conducted to understand the effect of bond force on thin die stacked assembly Pb-free microbumps is also reported. Results showed that optimum bond force is important to ensure no die cracks during flip chip bonding for 3 layer stacked die. In addition to the DOE conducted to understand the effect of bonding parameters on thin stacked die assembly, the selection of flux in terms of flux tackiness, flux for good solder wetting and minimum solder voids in the flip chip assembly were also addressed in this work. Low standoff for microjoint assembly often poses a challenge for underfill dispensing process. The standoff between the microbump joint of the chip on chip flip chip bonding is usually about 15µm to 20µm. The dispensing space is tight and often with limitations on the area where underfill fluids can be dispensed. Therefore it is important to evaluate flowability, bleeding of the underfill and the void formation in the underfill for stacked die assembly. The impact of these various factors on the stacked die assembly was discussed in this paper. Finally moldable underfill is then used to encapsulate the 3 layer stacked chip on the substrate. [ABSTRACT FROM PUBLISHER]

Published
2011
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