Search

In this paper, we propose a fast and accurate thermal aware analytical placer. Thermal model is constructed based on Green function with enhanced DCT to generate full chip temperature profile. Unlike other previous thermal aware placers, our thermal model is tightly integrated with a flat force directed placement. A thermal spreading force based on 2D Gaussian model is proposed to reduce maximum on-chip temperature with dynamic hot region size control, optimizing between total half-perimeter wirelength (HPWL) and on-chip temperature distribution. Our thermal model is evaluated by the most recent commercial tool and has an average deviation of 6.5% with 242× speed up. Our placer can reach the same quality compared to Capo and APlace2 with 2–3× speed up. Experiments are tested using ISPD 2005 benchmark with up to 2 million gate design. The results are further evaluated using GSRC Bookshelf Evaluator for total HPWL, and using ICEPAK for temperature distribution. To the best of our knowledge, this is the first thermal-aware placer using analytical thermal model and experimented on large scale design. It takes 6.5 hours to complete entire 2005 ISPD benchmark using our thermal aware placer. [ABSTRACT FROM PUBLISHER]