28 results on '"Pamunuwa D"'
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2. On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits
3. Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning.
4. 3-D integration and the limits of silicon computation.
5. Optimal signaling techniques for Through Silicon Vias in 3-D integrated circuit packages.
6. Analytic modeling of interconnects for deep sub-micron circuits
7. Scalability of network-on-chip communication architecture for 3-D meshes.
8. Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits.
9. Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh.
10. Design of robust molecular electronic circuits.
11. Molecular electronics device modeling for system design.
12. Delay-Balanced Smart Repeaters for On-Chip Global Signaling.
13. Nanodevices: from novelty toys to functional devices - an integration perspective.
14. Crosstalk immune interconnect driver design.
15. On dynamic delay and repeater insertion in distributed capacitively coupled interconnects.
16. Repeater insertion to minimise delay in coupled interconnects.
17. Accurate a priori signal integrity estimation using a multilevel dynamic interconnect model for deep submicron VLSI design.
18. On dynamic delay and repeater insertion
19. Closed form metrics to accurately model the response in general arbitrarily-coupled RC trees
20. A global wire planning scheme for Network-on-Chip
21. Repeater insertion to minimise delay in coupled interconnects
22. On dynamic delay and repeater insertion in distributed capacitively coupled interconnects
23. Memory Technology for Extended Large-Scale Integration in Future Electronics Applications.
24. A global wire planning scheme for Network-on-Chip.
25. Closed form metrics to accurately model the response in general arbitrarily-coupled RC trees.
26. Optimising bandwidth over deep sub-micron interconnect.
27. On dynamic delay and repeater insertion.
28. Combating digital noise in high speed ULSI circuits using binary BCH encoding.
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