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Your search keyword '"Lo W.-C."' showing total 21 results
Start Over Author "Lo W.-C." Publication Type Conference Materials
21 results on '"Lo W.-C."'

1. Development of Highly Manufacturable, Reliable, and Energy-Efficient Spin-Orbit Torque Magnetic Random Access Memory (SOT-MRAM)

Author

Rahaman, S. Z., primary, Chang, Y.-J., additional, Hsin, Y.-C., additional, Yang, S.-Y., additional, Chen, F.-M., additional, Chen, K.-M., additional, Wang, I-J., additional, Lee, H.-H., additional, Chen, G.-L., additional, Su, Y.-H., additional, Shih, C.-Y., additional, Chiu, S.-C., additional, Wei, J.-H., additional, Yen, S.-C., additional, Huang, K.-C., additional, Chen, C.-C., additional, Chen, M.-C., additional, Sheu, S.-S., additional, Lo, W.-C., additional, Chang, S.-Z., additional, See, Y.-C., additional, Deng, D.-L., additional, and Wu, C.-I, additional

Published
2022
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3. 3D Scalable, Wake-up Free, and Highly Reliable FRAM Technology with Stress-Engineered HfZrOx

Author

Lin, Y. D., primary, Sheu, S. S., additional, Hou, T. H., additional, Lo, W. C., additional, Lee, M. H., additional, Chang, M. F., additional, King, Y. C., additional, Lin, C. J., additional, Lee, H. Y., additional, Tang, Y. T., additional, Yeh, P. C., additional, Yang, H. Y., additional, Yeh, P. S., additional, Wang, C. Y., additional, Su, J. W., additional, and Li, S. H., additional

Published
2019
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7. Process integration for backside illuminated image sensor stacked with Analog-to-Digital Conversion chip

Author

Chang, H. H., primary, Chien, C. H., additional, Lee, Y. C., additional, Lee, S. M., additional, Wang, J. C., additional, Huang, Y. W., additional, Zhan, C. J., additional, Hsiao, Z. C., additional, Tzeng, P. J., additional, Lee, C. H., additional, Chen, T. S., additional, Ko, C. T., additional, Lo, W. C., additional, and Kao, M. J., additional

Published
2014
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13. Structural design, process, and reliability of a wafer-level 3D integration scheme with Cu TSVs based on micro-bump/adhesive hybrid wafer bonding

Author

Ko, C. T., primary, Hsiao, Z. C., additional, Chang, Y. J., additional, Chen, P. S., additional, Huang, J. H., additional, Fu, H. C., additional, Huang, Y. J., additional, Chiang, C. W., additional, Lee, C. K., additional, Chang, H. H., additional, Tsai, W. L., additional, Chen, Y. H., additional, Lo, W. C., additional, and Chen, K. N., additional

Published
2012
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16. Cu-based bonding technology for 3D integration applications

Author

Chen, K. N., primary, Xu, Z., additional, Liu, F., additional, Ko, C. T., additional, Cheng, C. A., additional, Huang, W. C., additional, Lin, H. L., additional, Cabral, C., additional, Hsiao, Z. C., additional, Klymko, N., additional, Fu, H. C., additional, Chen, Y. H., additional, Lu, J. Q., additional, and Lo, W. C., additional

Published
2012
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20. Cu-based bonding technology for 3D integration applications.

Author

Chen, K. N., Xu, Z., Liu, F., Ko, C. T., Cheng, C. A., Huang, W. C., Lin, H. L., Cabral, C., Hsiao, Z. C., Klymko, N., Fu, H. C., Chen, Y. H., Lu, J. Q., and Lo, W. C.

Abstract

This paper summarizes and reports systematical studies of Cu-based bonding technology for 3D IC applications. Hybrid Cu-oxide and Cu-polymer bonding designs and schemes are investigated. Electrical performances and reliability of Cu bond structures provide important guidelines for future 3D IC applications. [ABSTRACT FROM PUBLISHER]

Published
2011
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21. Wafer-level 3D integration with Cu TSV and micro-bump/adhesive hybrid bonding technologies.

Author

Ko, C. T., Hsiao, Z. C., Chang, Y. J., Chen, P. S., Huang, J. H., Fu, H. C., Huang, Y. J., Chiang, C. W., Tsat, W. L., Chen, Y. H., Lo, W. C., and Chen, K. N.

Abstract

Cu TSV combination with Cu/Sn micro-joint to form vertical interconnection is a good alternative for 3D integration. The insertion loss of two chip stack was evaluated by simulation to realize the signal transmission effects in high speed digital signaling via TSV and micro-joint interconnect. To satisfy the throughput and cost requirement for mass production in future, a wafer-level 3D integration scheme with Cu TSVs based on Cu/Sn micro-bump and BCB adhesive hybrid bonding was demonstrated. Key techniques including TSV fabrication, micro-bumping, hybrid bonding, wafer thinning and backside RDL formation were well developed and integrated to perform the 3D integration scheme. This paper presents a complete study of structure design, process condition, electrical and reliability assessment of the wafer-level 3D integration scheme. The 3D integration scheme was assessed to be with excellent electrical performance and reliability, and is potentially to be applied for 3D IC applications. [ABSTRACT FROM PUBLISHER]

Published
2011
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