179 results on '"Li, Xueqing"'
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2. A 28nm 8928Kb/mm2-Weight-Density Hybrid SRAM/ROM Compute-in-Memory Architecture Reducing >95% Weight Loading from DRAM
3. 34.7 A 28nm 2.4Mb/mm2 6.9 - 16.3TOPS/mm2 eDRAM-LUT-Based Digital-Computing-in-Memory Macro with In-Memory Encoding and Refreshing
4. 30 Mb/mm2/layer 3D eDRAM Computing-in-Memory with Embedded BEOL Peripherals and Local Layer-wise Calibration based on First-Demonstrated Vertically-stacked CAA-IGZO 4F2 2T0C Cell
5. Drivable Area Segmentation Based on HybridNets and Text Prompt Network
6. A Novel Fault Diagnosis Method Based on Feature Fusion and Model Agnostic Meta-Learning
7. ASMCap: An Approximate String Matching Accelerator for Genome Sequence Analysis Based on Capacitive Content Addressable Memory
8. Victor: A Variation-resilient Approach Using Cell-Clustered Charge-domain computing for High-density High-throughput MLC CiM
9. Design Exploration of Dynamic Multi-Level Ternary Content-Addressable Memory Using Nanoelectromechanical Relays
10. Fe-GCN: A 3D FeFET Memory Based PIM Accelerator for Graph Convolutional Networks
11. A 5.6-89.9TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro
12. 7.3 A 28nm 38-to-102-TOPS/W 8b Multiply-Less Approximate Digital SRAM Compute-In-Memory Macro for Neural-Network Inference
13. A 28nm 16.9-300TOPS/W Computing-in-Memory Processor Supporting Floating-Point NN Inference/Training with Intensive-CIM Sparse-Digital Architecture
14. On the Write Schemes and Efficiency of FeFET 1T NOR Array for Embedded Nonvolatile Memory and Beyond
15. Distributionally Robust Planning of Distribution Network Considering Flexibility of DSR
16. Hidden-ROM
17. High-density energy-efficient charge-domain computing based on CAA-IGZO TFT with BEOL-compatible 3D integration
18. Software Reliability Evaluation System of Ship Information Management System
19. Application of Software Cost Measurement in the Construction of Ship Information Management System
20. CREAM
21. YOLoC
22. An 8T/Cell FeFET-Based Nonvolatile SRAM with Improved Density and Sub-fJ Backup and Restore Energy
23. Low-Power and Scalable Retention-Enhanced IGZO TFT eDRAM-Based Charge-Domain Computing
24. The design and realization of performance test of video apps based on Android
25. Research on Operation Optimization of Active Distribution Networks Based on Multi-Port SOP Integrated Energy Storage System
26. Research on Power Balance Control Strategy of Three-phase CHB Photovoltaic Inverter
27. A Control Strategy of Photovoltaic Grid-connected Inverter Based on Active Power Reserve
28. A 16-Bit 4.0-GS/s Calibration-Free 65nm DAC with >70dBc SFDR and <-80dBc IM3 up to 1GHz Using Constant-Activity Element Switching
29. Exploiting FeFET Switching Stochasticity for Low-Power Reconfigurable Physical Unclonable Function
30. High Area/Energy Efficiency RRAM CNN Accelerator with Pattern-Pruning-Based Weight Mapping Scheme
31. UGRec: Modeling Directed and Undirected Relations for Recommendation
32. Capacitive Content-Addressable Memory
33. Construction of Chinese Freshwater Fish Information Database
34. Almost-Nonvolatile IGZO-TFT-Based Near-Sensor In-Memory Computing
35. Reducing Signal Swing Overheads to Only 8% in Background 3rd-Order Inter-Stage Gain Error Calibration for Pipeline ADCs
36. Dynamic Switching Sequence to Compensate the Integral Nonlinearity in Current-Steering DACs
37. Time Series Classification via Enhanced Temporal Representation Learning
38. 15.2 A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating
39. Dynamic Ternary Content-Addressable Memory Is Indeed Promising: Design and Benchmarking Using Nanoelectromechanical Relays
40. A Novel Network Traffic Anomaly Detection Approach Using the Optimal $\varphi$-DTW
41. Design Insights of Non-volatile Processors and Accelerators in Energy Harvesting Systems
42. FeFET-based low-power bitwise logic-in-memory with direct write-back and data-adaptive dynamic sensing interface
43. High PE Utilization CNN Accelerator with Channel Fusion Supporting Pattern-Compressed Sparse Neural Networks
44. A Comprehensive Model for Ferroelectric FET Capturing the Key Behaviors: Scalability, Variation, Stochasticity, and Accumulation
45. Integrated CAM-RAM Functionality using Ferroelectric FETs
46. Design of Almost-Nonvolatile Embedded DRAM Using Nanoelectromechanical Relay Devices
47. 14.2 A 65nm 24.7µJ/Frame 12.3mW Activation-Similarity-Aware Convolutional Neural Network Video Processor Using Hybrid Precision, Inter-Frame Data Reuse and Mixed-Bit-Width Difference-Frame Data Codec
48. 14.3 A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse
49. WSN Signal Reconstruction Based on Unknown Sparse Compressed Sensing
50. Adaptive Circuit Approaches to Low-Power Multi-Level/Cell FeFET Memory
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