62 results on '"Jinghong Chen"'
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2. PreFLMR: Scaling Up Fine-Grained Late-Interaction Multi-modal Retrievers.
3. A 4.8 GS/s 11b Time-Interleaved TDC-Assisted SAR ADC with High-Speed Latch-based VTC.
4. A 88%-Peak-Efficiency 10-mV-Voltage-Ripple Dual-Mode Switched-Capacitor DC-DC Converter for Ultra-Low-Power Battery Management.
5. A High-Gain and Low-Noise Mixer with Hybrid $G_{m}$-Boosting for 5G FR2 Applications.
6. A 3.84 GHz 32 fs RMS Jitter Over-Sampling PLL with High-Gain Cross-Switching Phase Detector.
7. A 400-MS/s 10-Bit SAR-Assisted Two-Step Digital-Slope ADC.
8. Grounding Description-Driven Dialogue State Trackers with Knowledge-Seeking Turns.
9. Fine-grained Late-interaction Multi-modal Retrieval for Retrieval Augmented Visual Question Answering.
10. A Real-time Respiration Monitoring System Using WiFi-Based Radar Model.
11. A 71-86 GHz Cascaded Harmonic Enhanced Tripler with -69 dBc Fundamental and -66 dBc Second Harmonic Suppression.
12. A 23.4-27.6 GHz 'Zig-Zag' VCO with Continuous Frequency Switching for FMCW Radars.
13. A 22-33 GHz Wideband CMOS LNA Using Low-k Non-inverting MCCRs for 5G mmW Communication Applications.
14. A 64-84 GHz CMOS LNA with Excellent Gain Flatness for Wideband mmW Applications.
15. An Automatic Comparator Offset Calibration for High-Speed Flash ADCs in FDSOI CMOS Technology.
16. A Quadrature Frequency Synthesizer with 118.7-fs Jitter, 27.94% Locking Range for Multiband 5G mmW Applications.
17. A 6-b 20-GS/s 2-Way Time-Interleaved Flash ADC with Automatic Comparator Offset Calibration in 28-nm FDSOI.
18. Machine-Learning Based Nonlinerity Correction for Coarse-Fine SAR-TDC Hybrid ADC.
19. A 500 MS/s 10-Bit Single-Channel SAR ADC with A Double-Rate Comparator.
20. A 1-GS/s 8-Bit 12.01-fJ/conv.-step Two-Step SAR ADC in 28-nm FDSOI Technology.
21. A 2.4 GS/s 10-Bit Time-Interleaved SAR ADC with a Bypass Window and Opportunistic Offset Calibration.
22. A Low-Power SiPM Readout Front-End with Fast Pulse Generation and Successive-Approximation Register ADC in 0.18 μm CMOS.
23. A 500-MS/s 13-Bit SAR-Assisted Time-Interleaved Digital-Slope ADC.
24. A Current Reuse Wideband LNA with Complementary Noise and Distortion Cancellation for Ultrasound Imaging Applications.
25. A 25-GS/s 4-bit Single-core Flash ADC in 28 nm FDSOI CMOS.
26. A Bandwidth-Tracking Self-Biased 5-to-2800 MHz Low-Jitter Clock Generator in 55nm CMOS.
27. A 14-bit 2.5 GS/s digital pre-distorted DAC in 65 nm CMOS with SFDR > 70 dB up to 1.2 GHz.
28. A 10-bit 400 MS/s asynchronous SAR ADC using dual-DAC architecture for speed enhancement.
29. RFI mitigating receiver back-end for radiometers.
30. Wideband LNA with 1.9 dB noise figure in 0.18 µm CMOS for high frequency ultrasound imaging applications.
31. A 21-Gb/s, 0.96-pJ/bit serial receiver with non-50% duty-cycle clocking 1-tap decision feedback equalizer in 65nm CMOS.
32. A 150 MHz bandwidth continuous-time ΔΣ modulator in 28 nm CMOS with DAC calibration.
33. Wireless networking testbed and emulator (WiNeTestEr).
34. Wideband LNA and multi-standard frequency synthesizer for reconfigurable radio.
35. A radiation-hardened DLL with fine resolution and DCC for DDR2 memory interface in 0.13 μm CMOS.
36. A 12b 60MS/s SHA-less opamp-sharing pipeline A/D with switch-embedded dual input OTAs.
37. A time-to-digital converter based AFC for wideband frequency synthesizer.
38. An all-CMOS low supply voltage temperature sensor front-end with error correction techniques.
39. A power-optimized reconfigurable CT ΔΣ modulator in 65nm CMOS.
40. A PVT-robust current-mode passive mixer with source-degenerated transconductance amplifier.
41. A radiation-tolerant ring oscillator phase-locked loop in 0.13µm CMOS.
42. A 30mW 10b 250MS/s dual channel SHA-less pipeline ADC in 0.18µm CMOS.
43. Infrequent Purchased Product Recommendation Making Based on User Behaviour and Opinions in E-commerce Sites.
44. An integrated CMOS transceiver for a 40Gb/s SCM optical communication system.
45. Model-order reduction of nonlinear MEMS devices through arclength-based Karhunen-Loeve decomposition.
46. An algorithm for automatic model-order reduction of nonlinear MEMS devices.
47. A mixed frequency-time approach for quasi-periodic steady-state simulation of multi-level modeled circuits.
48. The role of intermolecular interactions in fabricating hardened electro-optic materials.
49. A 150 MHz bandwidth continuous-time ΔΣ modulator in 28 nm CMOS with DAC calibration.
50. A low-latency, small-form-factor optical link for the high-luminosity LHC experiments.
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