195 results on '"Hong, Xianlong"'
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2. Congestion-driven floorplanning based on two-stage optimization
3. Fast placement for large-scale hierarchical FPGAs
4. Integrated interlayer via planning and pin assignment for 3D ICs
5. Cell shifting aware of wirelength and overlap
6. Incremental power optimization for multiple supply voltage design
7. Simultaneous buffer and interlayer via planning for 3D floorplanning
8. Efficient power network analysis with complete inductive modeling
9. A novel thermal optimization flow using incremental floorplanning for 3D ICs
10. Multi-objective Floorplanning Based on Fuzzy Logic
11. Modern Floorplanning with Boundary Clustering Constraint
12. Wirelength Optimization for Multilevel Hierachical FPGA
13. An efficient thermal optimization flow using incremental floorplanning for 3D microprocessors
14. Full-chip routing system for reducing Cu CMP & ECP variation
15. A novel performance driven power gating based on distributed sleep transistor network
16. Activity and register placement aware gated clock network design
17. IPOSA: A Novel Slack Distribution Algorithm for Interconnect Power Optimization
18. DFM Based Detailed Routing Algorithm for ECP and CMP
19. Efficient Thermal Aware Placement Approach Integrated with 3D DCT Placement Algorithm
20. Fast Wirelength-driven Partition-based Placement for Island Style FPGAs
21. A Low-Power Buffered Tree Construction Algorithm Aware of Supply Voltage Variation
22. Multilevel Based Global Routing Algorithm for Hierarchical FPGA
23. Thermal Effects with Leakage Power Considered in 2D/3D Floorplanning
24. Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building
25. Unified Quadratic Programming Approach For 3-D Mixed Mode Placement
26. Effective Acceleration of Iterative Slack Distribution Process
27. A Fast 3D-BSG Algorithm for 3D Packing Problem
28. Statistical Model Order Reduction for Interconnect Circuits Considering Spatial Correlations
29. An accurate and efficient probabilistic congestion estimation model in x architecture
30. Dummy fill aware buffer insertion during routing
31. Physical aware clock skew rescheduling
32. An effective buffer planning algorithm for IP based fixed-outline SOC placement
33. New timing and routability driven placement algorithms for FPGA synthesis
34. Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture
35. Power Delivery Aware Floorplanning for Voltage Island Designs
36. Congestion Driven Buffer Planning for X-Architecture
37. Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning
38. Interconnect Power Optimization Based on Timing Analysis
39. CMP-aware Maze Routing Algorithm for Yield Enhancement
40. Logic and Layout Aware Voltage Island Generation for Low Power Design
41. Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction
42. DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm
43. DFM-aware Routing for Yield Enhancement
44. Variational Circuit Simulator based on a Unified Methodology using Arithmetic over Taylor Polynomials
45. A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints
46. Source-code-level Transformation and APT-Driven Parallelism Pre-processes for Embedded System Automated Design
47. A Thermal-Driven Force-Directed Macro Cell Placement Algorithm
48. Interval Valued Variational Analysis Using the Arithmetic of Higher Order Polynomial
49. Congestion-Driven Placement Improvement Using Cell Spreading
50. A Fast Data Structure for HPWL Based on Reusablity Analysis
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