23 results on '"Gaioni, Luigi"'
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2. Design and test of current-mode DACs for threshold tuning of front-end channels for the High Luminosity LHC
3. Algorithms for Threshold Dispersion Minimization of the CHIPIX65 Asynchronous Front-End
4. Results from CHIPIX-FE0, a Small-Scale Prototype of a New Generation Pixel Readout ASIC in 65 nm CMOS for HL-LHC
5. Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors
6. Characterization of SLVS Driver and Receiver in a 65 nm CMOS Technology for High Energy Physics Applications
7. Total ionizing dose effects on CMOS devices in a 110 nm technology
8. Design of analog front-ends for the RD53 demonstrator chip
9. Charge preamplifier in a 65 nm CMOS technology for pixel readout in the Grad TID regime
10. Low-noise fast charge sensitive amplifier with dynamic signal compression
11. Active pixel sensors with enhanced pixel-level analog and digital functionalities in a 2-tier 3D CMOS technology
12. Perspectives of 65nm CMOS technologies for high performance front-end electronics
13. Monolithic pixel sensors for fast particle trackers in a quadruple well CMOS technology
14. CMOS MAPS in a homogeneous 3D process for charged particle tracking
15. Vertical integration approach to the readout of pixel detectors for vertexing applications
16. Analog design criteria for high-granularity detector readout in the 65 nm CMOS technology
17. Analog front-end for monolithic and hybrid pixels in a vertical integration CMOS technology
18. CMOS monolithic sensors in a homogeneous 3D process for low energy particle imaging
19. MAPS with pixel level sparsified readout: from standard CMOS to vertical integration
20. Review of radiation effects leading to noise performance degradation in 100 - nm scale microelectronic technologies
21. Investigating degradation mechanisms in 130 nm and 90 nm commercial CMOS technologies exposed to up to 100 Mrad ionizing radiation dose
22. Perspectives for low noise detector readout in a sub-quarter-micron CMOS SOI technology
23. Characterization of a large scale DNW MAPS fabricated in a 3D integration process.
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