32 results on '"Doria, Rodrigo T."'
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2. Experimental Analysis of HfO2/X ReRAM devices by the Capacitance Measurements
3. Standard MOS Diodes Composed by SOI UTBB Transistors
4. Junctionless Nanowire Transistor for Analog Applications: Cascode Current Mirror Configuration
5. Ultra-Low-Power Diodes Composed by SOI UTBB Transistors
6. SOI UTBB Capacitive Cross-Coupling Effects in Ultimate Technological Nodes
7. Junctionless Nanowire Transistors Based Wilson Current Mirror Configuration
8. Junctionless Nanowire Transistors Based Common-Source Current Mirror
9. Thermal Cross-Coupling Effects Analysis in UTBB Transistors
10. Analysis of the Thermal Properties of Self-Cascode Structures Composed by UTBB Transistors
11. Analysis of the substrate effect by the capacitive coupling in SOI UTBB Transistors
12. Analysis of the Output Conductance Degradation With the Substrate Bias in SOI UTB and UTBB Transistors
13. Adaption of triple gate junctionless MOSFETs analytical compact model for accurate circuit design in a wide temperature range
14. Lateral spacers influence on the effective channel length of junctionless nanowire transistors
15. A new method for junctionless transistors parameters extraction
16. Analysis of p-type Junctionless nanowire transistors with different crystallographic orientations
17. Analysis of the substrate bias effect on the thermal properties of SOI UTBB transistors
18. Influence of the crystal orientation on the operation of junctionless nanowire transistors
19. Physical insights on the dynamic response of junctionless nanowire transistors
20. A new series resistance extraction method for junctionless nanowire transistors
21. Effect of channel doping concentration on the harmonic distortion of asymmetric n- and p-type self-cascode MOSFETs
22. Effective channel length in Junctionless Nanowire Transistors
23. Use of back gate bias to enhance the analog performance of planar FD and UTBB SOI transistors-based self-cascode structures
24. Effect of the temperature on on Junctionless Nanowire Transistors electrical parameters down to 4K
25. Effective mobility analysis of n- and p-types SOI junctionless nanowire transistors
26. Temperature and back-gate bias influence on the operation of lateral SOI PIN photodiodes
27. Analog operation of Junctionless Nanowire Transistors down to liquid helium temperature
28. The influence of the substrate bias in Junctionless nanowire transistors
29. Non-linear behavior of Junctionless nanowire transistors operating in the linear regime
30. Effective channel length in Junctionless Nanowire Transistors.
31. Effect of channel doping concentration on the harmonic distortion of asymmetric n- and p-type self-cascode MOSFETs.
32. Use of back gate bias to enhance the analog performance of planar FD and UTBB SOI transistors-based self-cascode structures.
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