9 results on '"Dong-Hui Wang"'
Search Results
2. A hardware approach to reconfigurable lossless real-time tracer
3. Design and Implementation of a 64/32-bit Floating-point Division, Reciprocal, Square root, and Inverse Square root Unit
4. Design and implementation of a dynamic loop buffer by reusing the instruction buffer.
5. A 1.1 GHz 8B/10B encoder and decoder design.
6. A low-power 8-read 4-write register file design.
7. A 10MHz to 600MHz low jitter CMOS PLL for clock multiplication.
8. A low-power CMOS ASK clock and data recovery circuit for cochlear implants.
9. Crosstalk Prevention and Reduction in SuperV Back-end Design.
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.