Search

Your search keyword '"Devriendt, K."' showing total 84 results

Search Constraints

Start Over You searched for: Author "Devriendt, K." Remove constraint Author: "Devriendt, K." Publication Type Conference Materials Remove constraint Publication Type: Conference Materials
84 results on '"Devriendt, K."'

Search Results

1. Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails

2. Buried Power Rail Metal exploration towards the 1 nm Node

3. 60 Comprehensive genome-wide analysis of non-invasive test data allows accurate cancer prediction: a retrospective analysis of over 85.000 pregnancies

4. Buried Power Rail Scaling and Metal Assessment for the 3 nm Node and Beyond

5. Wafer-scale integration of double gated WS2-transistors in 300mm Si CMOS fab

6. Inflection points in interconnect research and trends for 2nm and beyond in order to solve the RC bottleneck

7. Scaled transistors with 2D materials from the 300mm fab

8. First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers

9. Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node

10. 3D Sequential Low Temperature Top Tier Devices using Dopant Activation with Excimer Laser Anneal and Strained Silicon as Performance Boosters

11. Vertical Nanowire and Nanosheet FETs: Device Features, Novel Schemes for Improved Process Control and Enhanced Mobility, Potential for Faster & More Energy Efficient Circuits

12. Scaled, Novel Effective Workfunction Metal Gate Stacks for Advanced Low-VT, Gate-All-Around Vertically Stacked Nanosheet FETs with Reduced Vertical Distance between Sheets

13. IGZO Integration Scheme For Enabling IGZO nFETs

14. Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications

15. 12-EUV Layer Surrounding Gate Transistor (SGT) for Vertical 6-T SRAM: 5-nm-class Technology for Ultra-Density Logic Devices

16. First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers

17. Vertically Stacked Gate-All-Around Si Nanowire CMOS Transistors with Reduced Vertical Nanowires Separation, New Work Function Metal Gate Solutions, and DC/AC Performance Optimization

18. Key challenges and opportunities for 3D sequential integration

19. DTCO and TCAD for a 12 Layer-EUV Ultra-Scaled Surrounding Gate Transistor 6T-SRAM

20. 3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability

21. Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling

25. Vertically stacked gate-all-around Si nanowire transistors: Key Process Optimizations and Ring Oscillator Demonstration

26. WS2 transistors on 300 mm wafers with BEOL compatibility

27. Strained germanium gate-all-around PMOS device demonstration using selective wire release etch prior to replacement metal gate deposition

28. BEOL compatible WS2 transistors fully fabricated in a 300 mm pilot line

29. N5 technology node dual-damascene interconnects enabled using multi patterning

30. In Depth Analysis of 3D NAND Enablers in Gate Stack Integration and Demonstration in 3D Devices

32. Improvement of the CMOS characteristics of bulk Si FinFETs by high temperature ion implantation

33. Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates

34. Challenges and opportunities of vertical FET devices using 3D circuit design layouts

35. Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates

36. Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells

37. Scalability of InGaAs gate-all-around FET integrated on 300mm Si platform: Demonstration of channel width down to 7nm and Lg down to 36nm

38. Si-cap-free SiGe p-channel FinFETs and gate-all-around transistors in a replacement metal gate process: Interface trap density reduction and performance improvement by high-pressure deuterium anneal

39. Gate-all-around NWFETs vs. triple-gate FinFETs: Junctionless vs. extensionless and conventional junction devices with controlled EWF modulation for multi-VT CMOS

40. RMG nMOS 1st process enabling 10x lower gate resistivity in N7 bulk FinFETs

41. Highly scalable bulk FinFET Devices with Multi-VT options by conductive metal gate stack tuning for the 10-nm node and beyond

42. Performance and reliability of high-mobility Si0.55Ge0.45 p-channel FinFETs based on epitaxial cladding of Si Fins

43. A new complementary hetero-junction vertical Tunnel-FET integration scheme

45. Thermal and Plasma Treatments for Improved (Sub-)1nm EOT Planar and FinFET-based RMG High-k Last Devices and Enabling a Simplified Scalable CMOS Integration Scheme

46. W vs. Co-Al as Gate Fill-Metal for Aggressively Scaled Replacement High-k/Metal Gate Devices for (Sub-)22nm Tech. Nodes

47. RMG Tech. Integration in FinFET Devices

48. Effective Work Function Engineering for Aggressively Scaled Planar and FinFET-based Devices with High-k Last Replacement Metal Gate Tech.

50. Process control & integration options of RMG technology for aggressively scaled devices

Catalog

Books, media, physical & digital resources