1. Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails
- Author
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Veloso, A., primary, Jourdain, A., additional, Radisic, D., additional, Chen, R., additional, Arutchelvan, G., additional, O'Sullivan, B., additional, Arimura, H., additional, Stucchi, M., additional, Keersgieter, A. De, additional, Hosseini, M., additional, Hopf, T., additional, D'Have, K., additional, Wang, S., additional, Dupuy, E., additional, Mannaert, G., additional, Vandersmissen, K., additional, Iacovo, S., additional, Marien, P., additional, Choudhury, S., additional, Schleicher, F., additional, Sebaai, F., additional, Oniki, Y., additional, Zhou, X., additional, Gupta, A., additional, Schram, T., additional, Briggs, B., additional, Lorant, C., additional, Rosseel, E., additional, Hikavyy, A., additional, Loo, R., additional, Geypen, J., additional, Batuk, D., additional, Martinez, G. T., additional, Soulie, J. P., additional, Devriendt, K., additional, Chan, B. T., additional, Demuynck, S., additional, Hiblot, G., additional, der Plas, G. Van, additional, Ryckaert, J., additional, Beyer, G., additional, Litta, E. Dentoni, additional, Beyne, E., additional, and Horiguchi, N., additional
- Published
- 2022
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