67 results on '"Csaba Andras Moritz"'
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2. SkyBridge-3D-CMOS 2.0: IC Technology for Stacked-Transistor 3D ICs beyond FinFETs.
3. A Wafer-scale Manufacturing Pathway for Fine-grained Vertical 3D-IC Technology.
4. Accelerating Simulation-based Inference with Emerging AI Hardware.
5. Nano-Crossbar based Computing: Lessons Learned and Future Directions.
6. Reconfigurable Probabilistic AI Architecture for Personalized Cancer Treatment.
7. Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling.
8. Integrated Synthesis Methodology for Crossbar Arrays.
9. Structure Discovery for Gene Expression Networks with Emerging Stochastic Hardware.
10. Magneto-Electric Approximate Computational Circuits for Bayesian Inference.
11. Power-delivery network in 3D ICs: Monolithic 3D vs. Skybridge 3D CMOS.
12. SkyNet: Memristor-based 3D IC for artificial neural networks.
13. Routability in 3D IC design: Monolithic 3D vs. Skybridge 3D CMOS.
14. Towards automatic thermal network extraction in 3D ICs.
15. On the Design of Ultra-High Density 14nm Finfet Based Transistor-Level Monolithic 3D ICs.
16. Skybridge-3D-CMOS: A Vertically-Composed Fine-Grained 3D CMOS Integrated Circuit Technology.
17. Architecting 3-D integrated circuit fabric with intrinsic thermal management features.
18. Architecting NP-Dynamic Skybridge.
19. Architecting connectivity for fine-grained 3-D vertically integrated circuits.
20. Fine-grained 3-D integrated circuit fabric using vertical nanowires.
21. Wave-based multi-valued computation framework.
22. Experimental prototyping of beyond-CMOS nanowire computing fabrics.
23. Design of 8T-nanowire RAM array.
24. Spin wave nanofabric update.
25. Ternary volatile random access memory based on heterogeneous graphene-CMOS fabric.
26. Fine-grained 3D reconfigurable computing fabric with RRAM.
27. Parametrized hardware architectures for the Lucas primality test.
28. Biased Voting for Improved Yield in Nanoscale Fabrics.
29. Hybrid Graphene Nanoribbon-CMOS tunneling volatile memory fabric.
30. Spin wave functions nanofabric update.
31. N3ASICs: Designing nanofabrics with fine-grained CMOS integration.
32. Impact of nanomanufacturing flow on systematic yield losses in nanoscale fabrics.
33. Nanoscale Application Specific Integrated Circuits.
34. Incorporating Heterogeneous Redundancy in a Nanoprocessor for Improved Yield and Performance.
35. Parameter Variability in Nanoscale Fabrics: Bottom-Up Integrated Exploration.
36. Towards logic functions as the device.
37. Validating cascading of crossbar circuits with an integrated device-circuit exploration.
38. Power and performance tradeoffs with process variation resilient adaptive cache architectures.
39. CMOS Control Enabled Single-Type FET NASIC.
40. Combining 2-level logic families in grid-based nanoscale fabrics.
41. Designing Memory Subsystems Resilient to Process Variations.
42. Support for Fine-Grained Synchronization in Shared-Memory Multiprocessors.
43. Power and Failure Analysis of CAM Cells Due to Process Variations.
44. PARE: a power-aware hardware data prefetching engine.
45. Nanowire field-programmable computing platform.
46. Energy-Aware Data Prefetching for General-Purpose Programs.
47. Energy Characterization of Hardware-Based Data Prefetching.
48. Cool-Fetch: A Compiler-Enabled IPC Estimation Based Framework for Energy Reduction.
49. Opportunities and challenges in application-tuned circuits and architectures based on nanodevices.
50. Combining compiler and runtime IPC predictions to reduce energy in next generation architectures.
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