50 results on '"Benoît Dupont de Dinechin"'
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2. In-Place Multicore SIMD Fast Fourier Transforms.
3. Exact Fused Dot Product Add Operators.
4. A Posit8 Decompression Operator for Deep Neural Network Inference.
5. Computing In-Place FFTs with SIMD Lane Slicing.
6. Distortion Approximation of a Compressed Softmax Layer.
7. A study of predictable execution models implementation for industrial data-flow applications on a multi-core platform with shared banked memory.
8. Response time analysis of dataflow applications on a many-core processor with shared-memory and network-on-chip.
9. Embedded Runtime for Reconfigurable Dataflow Graphs on Manycore Architectures.
10. A Distributed Framework for Low-Latency OpenVX over the RDMA NoC of a Clustered Manycore.
11. Parallel code generation of synchronous programs for a many-core architecture.
12. Network-on-chip service guarantees on the kalray MPPA-256 bostan processor.
13. Hierarchical Dataflow Model for efficient programming of clustered manycore processors.
14. Feed-Forward Routing for the Wormhole Switching Network-on-Chip of the Kalray MPPA2 Processor.
15. Improving 3D lattice boltzmann method stencil with asynchronous transfers on many-core processors.
16. Asynchronous one-sided communications and synchronizations for a clustered manycore processor.
17. Paving the Way Towards a Highly Energy-Efficient and Highly Integrated Compute Node for the Exascale Revolution: The ExaNoDe Approach.
18. Engineering a Manycore Processor for Edge Computing.
19. Optimal and fast throughput evaluation of CSDF.
20. Kalray MPPA®: Massively parallel processor array: Revisiting DSP acceleration with the Kalray MPPA Manycore processor.
21. The shift to multicores in real-time and safety-critical systems.
22. MPI communication on MPPA Many-core NoC: design, modeling and performance issues.
23. Implementation of a Fast Fourier transform algorithm onto a manycore processor.
24. Guaranteed Services of the NoC of a Manycore Processor.
25. Time-critical computing on a single-chip massively parallel processor.
26. Using the SSA-Form in a Code Generator.
27. Consolidating High-Integrity, High-Performance, and Cyber-Security Functions on a Manycore Processor.
28. Periodic schedules for Cyclo-Static Dataflow.
29. A clustered manycore processor architecture for embedded and accelerated applications.
30. A Distributed Run-Time Environment for the Kalray MPPA®-256 Integrated Manycore Processor.
31. Extended Cyclostatic Dataflow Program Compilation and Execution for an Integrated Manycore Processor.
32. K-Periodic schedules for evaluating the maximum throughput of a Synchronous Dataflow graph.
33. A Non-iterative Data-Flow Algorithm for Computing Liveness Sets in Strict SSA Programs.
34. A mixed-precision fused multiply and add.
35. Co-Design and Abstraction of a Network-on-Chip Using Deterministic Network Calculus.
36. Revisiting Out-of-SSA Translation for Correctness, Code Quality and Efficiency.
37. Inter-block Scoreboard Scheduling in a JIT Compiler for VLIW Processors.
38. Fast liveness checking for ssa-form programs.
39. SCAN: A Heuristic for Near-Optimal Software Pipelining.
40. Division by Constant for the ST100 DSP Microprocessor.
41. Code generator optimizations for the ST120 DSP-MCU core.
42. Extending Modulo Scheduling with Memory Reference Merging.
43. A Unified Software Pipeline Construction Scheme for Modulo Scheduled Loops.
44. Definition of the F-- Extension to Fortran 90.
45. A Unified Software Pipeline Construction Scheme for Modulo Scheduled Loops.
46. Parametric Computation of Margins and of Minimum Cumulative Register Lifetime Dates.
47. Insertion Scheduling: An Alternative to List Scheduling for Modulo Schedulers.
48. An Introduction to Simplex Scheduling.
49. StaCS: a Static Control Superscalar architecture.
50. A ultra fast Euclidean division algorithm for prime memory systems.
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