46 results on '"Ao Ren"'
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2. DPC: DPU-accelerated High-Performance File System Client.
3. An FPGA-based kNN Seach Accelerator for point cloud registration.
4. Navigation of Tendon-driven Flexible Robotic Endoscope through Deep Reinforcement Learning.
5. SCRA: Systolic-Friendly DNN Compression and Reconfigurable Accelerator Co-Design.
6. RadarSSD: A Computational Storage for Radar Signal Processing.
7. Re-compact: Structured Pruning and SpMM Kernel Co-design for Accelerating DNNs on GPUs.
8. Data-Quality-Driven Federated Learning for Optimizing Communication Costs.
9. Optimizing the Incremental Update Mechanism by Inlaying File Indexes on Flash Storage.
10. An Efficient Scheduling Algorithm for Multi-mode Tasks on Near-Data Processing SSDs.
11. HBP: Hierarchically Balanced Pruning and Accelerator Co-Design for Efficient DNN Inference.
12. IFHE: Intermediate-Feature Heterogeneity Enhancement for Image Synthesis in Data-Free Knowledge Distillation.
13. Optimizing the Performance of NDP Operations by Retrieving File Semantics in Storage.
14. 3DS: An Efficient DPDK-based Data Distribution Service for Distributed Real-time Applications.
15. VEA: An FPGA-Based Voxel Encoding Accelerator for 3D Object Detection with LiDAR.
16. CADedup: High-performance Consistency-aware Deduplication Based on Persistent Memory.
17. Improving DNN Fault Tolerance using Weight Pruning and Differential Crossbar Mapping for ReRAM-based Edge AI.
18. FedSAE: A Novel Self-Adaptive Federated Learning Framework in Heterogeneous Systems.
19. CSAFL: A Clustered Semi-Asynchronous Federated Learning Framework.
20. DARB: A Density-Adaptive Regular-Block Pruning for Deep Neural Networks.
21. Measuring Data Reconstruction Defenses in Collaborative Inference Systems.
22. ADMM-NN: An Algorithm-Hardware Co-Design Framework of DNNs Using Alternating Direction Methods of Multipliers.
23. A Majority Logic Synthesis Framework for Adiabatic Quantum-Flux-Parametron Superconducting Circuits.
24. A stochastic-computing based deep learning framework using adiabatic quantum-flux-parametron superconducting technology.
25. A Buffer and Splitter Insertion Framework for Adiabatic Quantum-Flux-Parametron Superconducting Circuits.
26. IDE Development, Logic Synthesis and Buffer/Splitter Insertion Framework for Adiabatic Quantum-Flux-Parametron Superconducting Circuits.
27. VIBNN: Hardware Acceleration of Bayesian Neural Networks.
28. Structured Weight Matrices-Based Hardware Accelerators in Deep Neural Networks: FPGAs and ASICs.
29. Towards Budget-Driven Hardware Optimization for Deep Convolutional Neural Networks Using Stochastic Computing.
30. An area and energy efficient design of domain-wall memory-based deep convolutional neural networks using stochastic computing.
31. A 65nm 0.39-to-140.3TOPS/W 1-to-12b Unified Neural Network Processor Using Block-Circulant-Enabled Transpose-Domain Acceleration with 8.1 × Higher TOPS/mm2and 6T HBST-TRAM-Based 2D Data-Reuse Architecture.
32. SC-DCNN: Highly-Scalable Deep Convolutional Neural Network using Stochastic Computing.
33. Deep reinforcement learning: Framework, applications, and embedded implementations: Invited paper.
34. Softmax Regression Design for Stochastic Computing Based Deep Convolutional Neural Networks.
35. Memristor crossbar-based ultra-efficient next-generation baseband processors.
36. Hardware Acceleration of Bayesian Neural Networks Using RAM Based Linear Feedback Gaussian Random Number Generators.
37. Ultra-fast robust compressive sensing based on memristor crossbars.
38. Towards acceleration of deep convolutional neural networks using stochastic computing.
39. Algorithm-hardware co-optimization of the memristor-based framework for solving SOCP and homogeneous QCQP problems.
40. Structural design optimization for deep convolutional neural networks using stochastic computing.
41. Hardware-driven nonlinear activation for stochastic computing based deep convolutional neural networks.
42. Designing reconfigurable large-scale deep learning systems using stochastic computing.
43. DSCNN: Hardware-oriented optimization for Stochastic Computing based Deep Convolutional Neural Networks.
44. Memristor-Based Discrete Fourier Transform for Improving Performance and Energy Efficiency.
45. A low-computation-complexity, energy-efficient, and high-performance linear program solver using memristor crossbars.
46. Design of high-speed low-power polar BP decoder using emerging technologies.
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