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This paper presents the design of an analog front-end of a passive UHF RFID tag compliant with the EPCglobal Class 1 Generation 2 standard. To enable long-range operation of passive tags, the power consumption must be minimized. In this work, the front-end consumes 1uA at the minimum supply voltage of 1.2V and features a RF to DC rectification efficiency of 36.9%. As technology, a TowerJazz Standard Logic 0.18um process with Schottky diodes is used. Several energy-saving techniques are employed and explicated. A novel zero-to-absolute-temperature (ZTAT) structure is introduced, enabling the efficient generation of a stable clock frequency with ±1.8 % dynamic change. The backward signal power is examined and equals −75 dBm at a distance of 17m. The theoretical sensitivity of the analog front-end itself is −24 dBm. [ABSTRACT FROM PUBLISHER]

The analog front-end of an ECBM transceiver operating from a single 5-V supply is described. The chip performs pulse shaping and line driving in the transmit section with hybrid function, equalization, A/D (analog-to-digital), D/A automatic gain control, threshold detection for PLL (phase-locked loops) and weak-up in the receive section. The chip dissipates about 160 mW in normal operation mode and 7 mW in power-down mode. The die area is 50000 mil2 in a 2-μm, double-poly, single-metal CMOS technology [ABSTRACT FROM PUBLISHER]