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Nowadays, reconfigurable hardware is used in a broad range of use cases and applications. Therefore, hardware components need to operate reliably in a wide range of temperatures. The problem of heat dissipation is a widely discussed topic and has to be taken into account especially with the trend of smaller technologies being used to manufacture the chips. The uneven heat distribution and the temperature differences across the chip stress it in different ways so that an aging process could develop and contribute to a shorter lifespan of a product. One major problem is that on today's boards sensors occupy a relatively large amount of area on the chip. For this reason, the implementation of a monitoring process that is based on a simple design and does not consume too much power is proposed. This allows to determine uneven processes and would lead to the consequence to reconfigure the hardware for an optimal distribution of the heat. The paper proposes a method of on-chip temperature measurement and monitoring on reconfigurable hardware. The design explores an approach in which physical sensors are no longer needed. Additionally, the proposed system allows the measurement of on-chip temperature in any location of an FPGA. Subsequently, by placing the on-chip measurement system into strategic locations on the reconfigurable hardware, the presence of an on-chip temperature gradient is observed which could affect the reliability of critical designs. [ABSTRACT FROM PUBLISHER]

An accurate estimation of the success probability and data complexity of linear cryptanalysis is a fundamental question in symmetric cryptography. In this paper, we propose an efficient reconfigurable hardware architecture to compute the success probability and data complexity of Matsui's Algorithm 2 which is the central technique in linear cryptanalysis for block ciphers. Using this dedicated architecture, we are able to investigate the complexity of the algorithm for up to 40-bit block ciphers for low-correlation lineaer approximations and high advantages. Performing experiments on larger block lengths ensures that any empirical observations are not due to differences in statistical behavior for artificially small block lengths. Rather surprisingly, we observed in previous experiments a significant deviation between the theory and practice for Matsui's Algorithm 2 for larger block sizes in a vast range of parameters. The new hardware architecture allows us to verify the existing theoretical models for the complexity estimation in linear cryptanalysis. The designed hardware architecture is realized on two Xilinx Virtex-6 XC6VLX240T FPGAs for smaller block lengths, and on RIVYERA platform with 128 Xilinx Spartan-3 XC3S5000 FPGAs for larger block lengths. [ABSTRACT FROM PUBLISHER]

To further exploit the potential of reconfigurable computing, fine-grain, super massive parallel processing SAT solver over reconfigurable hardware accelerator is proposed in this paper as SMPP. By analyzing the traditional SAT solver, we proposed a novel way to partition the original problem into software part and hardware part. Software part uses semi-confliction guided backtrack to extract equivalent fixed scale sub-problem sequence. Partition scheme of SMPP exploited the stage effect of inference engine in modern software SAT solver. Hardware part uses tiny processing cells to handle small scale SAT problem in linear time proportional to the number of clause. Theoretical analyze and experiment results show that the speed up factor is significant. [ABSTRACT FROM PUBLISHER]

The PRESENT cipher is a symmetric block cipher with 64 bits of data block and 80 (or 128) bits of key. It is based on Substitution-permutation network and consists of 31 rounds. PRESENT is intended to be implemented in small embedded and contactless systems, thus its design needs only small amount of chip area and consumes low power. In this work we evaluate the resistance of PRESENT against time-memory trade-off attack. Specifically Rainbow Tables method is used. We determine the computational demand of this type of attack conducted on special parallel reconfigurable hardware COPACOBANA consisting of array of FPGA chips with custom design. [ABSTRACT FROM PUBLISHER]

The hardware/software implementation of a custom vision board using minimal resources out of a reconfigurable platform is described. Demanding robotic vision applications in most cases require dedicated hardware for reliable operation. The designed system is based on a Cyclone IV Altera FPGA device that constitutes the main processing unit of the reconfigurable hardware and on a 32 -- bit Microchip PIC32 micro controller as a complementary processor. The main goal of this research is to accelerate image processing algorithms using only minimal resources of the custom designed reconfigurable hardware. The micro controller serves peripheral control tasks, relieving valuable resources from the FPGA device. Video images are captured using a CMOS image sensor. USB connectivity with a personal computer is provided using a FIFO-to-USB module. Operational tasks such as frame grabbing, image filtering and USB communication are integrated to the system by implementing custom-designed controllers in VHDL. Image processing functions are accelerated using a fully parallel pipeline which is described analytically. A host computer interface has also been developed in order to test the overall system in action. The system is evaluated in terms of resource usage and the advantages emanating from the proposed architecture are discussed. [ABSTRACT FROM PUBLISHER]

This paper describes a design for a variable fractional delay (VFD) FIR filter implemented on reconfigurable hardware. Fractionally delayed signals are required for several audio-based applications, including echo cancellation and musical signal analysis. Traditionally, VFD FIR filters are implemented using a complex, fixed structure based upon the order of the filter. This fixed structure restricts the range of valid fractional delay values permitted by the filter. The proposed design in this paper implements an order-scalable FIR filter, permitting fractionally delayed signals of widely varying integer sizes. This design builds upon the traditional Lagrange interpolator FIR filter using either a software-based or hardware-based Lagrange coefficient computational unit. Using today's (2012) low-cost high performance reconfigurable hardware FIR coefficients can be computed fast enough for real-time variable fractional delay applications. The resulting real-time VFD FIR filter is tested using the Xilinx System Generator toolkit as well as Xilinx ISE and ModelSim. The proposed filter was functionally verified using ModelSim and System Generator. [ABSTRACT FROM PUBLISHER]

We present a novel framework to detect power attacks on crypto-systems implemented on reconfigurable hardware. We monitor the device supply voltage with a ring oscillator-based on-chip power monitor. In order to detect the insertion of power measurement circuits onto a device's power rail, a power attack detection strategy taking into account abnormal supply voltages and power rail resistance values is developed. Our strategy is integrated into an on-chip attack detector. The entire framework implementation only takes 3300 LUTs of a Spartan-6 LX45 FPGA, which is 12% of the total area available. Our results on an AES and RSA crypto-system show that our attack detection framework can reach false-positive and false-negative rates as low as 0% over all our test cases if proper operating margins are set. [ABSTRACT FROM PUBLISHER]

In this paper a novel modular superscalar execution core is presented for a medium grain reconfigurable hardware. The processor can be configured for varying path widths, reservation station depths, and reorder buffer sizes with minimal redesign effort. An analysis comparing the superscalar core with a five-stage execution core shows that a speedup of 2.073 can easily be achieved while increasing area by only 29%. [ABSTRACT FROM PUBLISHER]