1. Three-Dimensional Stacked Neural Network Accelerator Architectures for AR/VR Applications.
- Author
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Yang, Lita, Radway, Robert, Chen, Yu-Hsin, Wu, Tony, Liu, Huichu, Ansari, Elnaz, Chandra, Vikas, Mitra, Subhasish, and Beigne, Edith
- Subjects
- *
AUGMENTED reality , *VERTICAL integration , *VIRTUAL reality , *SYSTEMS on a chip - Abstract
Three-dimensional integration offers architectural and performance benefits for scaling augmented/virtual reality (AR/VR) models on highly resource-constrained edge devices. Two-dimensional off-chip memory interfaces are too prohibitively energy intensive and bandwidth (BW) limited for AR/VR devices. To solve this, we propose using advanced 3-D stacking technology for high-density vertical integration to local memory and compute, increasing memory capacity within the same footprint at iso-BW with improvements in energy and latency. We evaluate 3-D architectures for a prototype AR/VR accelerator to demonstrate up to 3.9× latency reduction and 1.6× lower energy compared to a 2-D configuration within a smaller/similar footprint. Additionally, we show the feasibility of deploying higher resolution AR/VR models by stacking multiple tiers of memory, providing a pathway to break the footprint constraints of 2-D architectures. The use of high-density 3-D interconnects allows us to demonstrate localized benefits at the accelerator-level compared with standard system-on-chip memory disaggregation techniques/architectures. [ABSTRACT FROM AUTHOR]
- Published
- 2022
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