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Xilinx System Generator (XSG) integrates with MATLAB Simulink to build a complex system through Xilinx and Simulink blocks. This paper presents a hardware implementation of various image processing techniques to modify and extract the pixel information from various input images in run time. Complex coding strategies are eradicated with integrated system. The intricacy in structural design is reduced to a huge extent using Xilinx System generator. The reconfigurable attribute of Field Programmable Gate Array (FPGA) bags the massive advantages in image processing like co simulating with selective pixel and verified on FPGA. Image processing algorithms explored in methodical manner by performing diverse operations like edge detection, and color enhancement, complement, contrast stretching etc. The proposed image processing techniques (IPT) intended for various applications. Dissimilar image processing techniques are processed by FPGA and displayed on Video Graphics Array (VGA). Image processing system is designed in XSG, hardware description language (HDL) like VHDL & Verilog code is generated by processing system by system generator token. Design is implemented on Artix-7 and targeted on Basys3 reconfigurable hardware (XC7A35T-1-CPG236C). [ABSTRACT FROM AUTHOR]

Robotic systems are used in many sectors, such as agriculture and industrial production, but new problems are emerging. This paper presents an offline, Spanning Tree Coverage algorithm that utilizes more parameters than existing algorithms. It has knowledge of the whole environment and is able to cope with new challenges and problems. The motivation for the proposed algorithm was the lack of efficient and up-to-date algorithms in the field of coverage path planning in robotics, as well as in the real time navigation of autonomous vehicles, both in known and unknown environments. This paper does not propose an algorithm but a system architecture that uses several metrics to generate the most appropriate path for each robot. [ABSTRACT FROM AUTHOR]

Internet of things (IoT) has become an easy target. As there are numerous devices, management is hard and security problems arise. There are various encryption algorithms to provide the security of data on an IoT device. One of the encryption algorithms that is used for IoT devices is the AES algorithm. Although the AES algorithm is not a lightweight algorithm, it can effectively be used to protect the data of IoT devices. In this paper, a Bluetooth Low Energy (BLE) module is used as an IoT device. The AES algorithm is used to encrypt the data that is generated on the BLE device. There are two options for encryption: hardware-based encryption and software-based one. The aim of the paper is to show the hardware implementation efficiency of the AES algorithm on an IoT device by comparing it with software implementation. As a result, the hardware implementation of the AES algorithm is efficient when using the proper hardware infrastructure. [ABSTRACT FROM AUTHOR]

Internet of things (IoT) has become an easy target. As there are numerous devices, management is hard and security problems arise. There are various encryption algorithms to provide the security of data on an IoT device. One of the encryption algorithms that is used for IoT devices is the AES algorithm. Although the AES algorithm is not a lightweight algorithm, it can effectively be used to protect the data of IoT devices. In this paper, a Bluetooth Low Energy (BLE) module is used as an IoT device. The AES algorithm is used to encrypt the data that is generated on the BLE device. There are two options for encryption: hardware-based encryption and software-based one. The aim of the paper is to show the hardware implementation efficiency of the AES algorithm on an IoT device by comparing it with software implementation. As a result, the hardware implementation of the AES algorithm is efficient when using the proper hardware infrastructure. [ABSTRACT FROM AUTHOR]

The paper selects reusable operations over binary and ternary vectors that are frequently used in many important practical applications (that are explicitly indicated) and suggests methods to implement them in hardware accelerators. Many examples are given. The developed architectures are organized as either combinational or sequential designs. The following steps are elaborated: 1) suggesting methods and architectures based on knowledge and the results of previous publications; 2) modeling in software and estimating the most important characteristics of the future circuits; 3) implementation in hardware, evaluation of the design, and experiments. The presented example demonstrates all these steps. The results of experiments show effectiveness of the proposed accelerators form the point of view of performance and the consumed resources. [ABSTRACT FROM AUTHOR]

In this paper, we present an implementation of Advanced Encryption Standard (AES) cryptographic algorithm using state-of-the-art Virtex-5 Field Programmable Gate Array (FPGA). The design is coded in Very High Speed Integrated Circuit Hardware Description Language (VHDL). Timing simulation is performed to verify the functionality of the designed circuit. Performance evaluation is also done in terms of throughput and area. The design implemented on Virtex-5 (XC5VLX50FFG676-3) FPGA achieves a maximum throughput of 4.34 Gbps utilizing a total of 399 slices. [ABSTRACT FROM AUTHOR]

The Data mining algorithms have become vital to researchers in science, engineering, medicine, business, search and security domains. In recent years, there has been a terrific raise in the size of the data being collected and analyzed. Classification is the main difficulty faced in data mining. In a number of the solutions developed for this problem, most accepted one is Decision Tree Classification (DTC) that gives high precision while handling very large amount of data. This paper presents VLSI implementation of flexible architecture for Decision Tree classification in data mining using c4.5 algorithm. [ABSTRACT FROM AUTHOR]

In Computer Science, the Boolean Satisfiability Problem(SAT) is the problem of determining if there exists an interpretation that satisfies a given Boolean formula. SAT is one of the first problems that was proven to be NP-complete, which is also fundamental to artificial intelligence, algorithm and hardware design. This paper reviews the main algorithms of the SAT solver in recent years, including serial SAT algorithms, parallel SAT algorithms, SAT algorithms based on GPU, and SAT algorithms based on FPGA. The development of SAT is analyzed comprehensively in this paper. Finally, several possible directions for the development of the SAT problem are proposed. [ABSTRACT FROM AUTHOR]

Optimization algorithms are often inspired by processes occuring in nature, such as animal behavioral patterns. The main concern with implementing such algorithms in software is the large amounts of processing power they require. In contrast to software code, that can only perform calculations in a serial manner, an implementation in hardware, exploiting the inherent parallelism of single-purpose processors, can prove to be much more effcient both in speed and energy consumption. Furthermore, the use of Cellular Automata (CA) in such an implementation would be effcient both as a model for natural processes, as well as a computational paradigm implemented well on hardware. In this paper, we propose a VHDL implementation of a metaheuristic algorithm inspired by the echolocation behavior of bats. More specifically, the CA model is inspired by the metaheuristic algorithm proposed earlier in the literature, which could be considered at least as effcient than other existing optimization algorithms. The function of the FPGA implementation of our algorithm is explained in full detail and results of our simulations are also demonstrated. [ABSTRACT FROM AUTHOR]

The Extreme Learning Machine (ELM) algorithm conventionally suffers from the inferior batch training performance. In this paper, a new approach to combine ELM outputs is proposed with a view to further develop a persistent IDS. Specifically, this paper proposes the application of an Extreme Learning Machine based approach to the network-based intrusion detection system (IDSs). Good performance is achieved and preliminary results are reported in this paper. [ABSTRACT FROM AUTHOR]

The Radiation Hardened Electronics for Space Environments (RHESE) project develops advanced technologies needed for high performance electronic devices that will be capable of operating within the demanding radiation and thermal extremes of the space, lunar, and Martian environment. The technologies developed under this project enhance and enable avionics within multiple mission elements of NASA's Vision for Space Exploration, including the Constellation program's Orion Crew Exploration Vehicle, the Lunar Lander project, Lunar Outpost elements, and Extra Vehicular Activity (EVA) elements. This paper provides an overview of the RHESE project and its multiple task tasks, their technical approaches, and their targeted benefits as applied to NASA missions. [ABSTRACT FROM AUTHOR]

Montgomery modular multiplication (MMM) plays a crucial role in the implementation of modular exponentiations of public-key cryptography. In this paper, we discuss the iterative structure and extend the iterative bound condition of MMM. It can be applied to complicated modular exponentiations. Based on the iterative condition of MMM, we can directly use non-modular additions, subtractions and even simple multiplications instead of the modular forms, which make modular exponentiation operation very efficient but more importantly iterative applicability of MMM. [ABSTRACT FROM AUTHOR]

Real-time control will play an important role in the operation and scientific exploitation of the new generation fusion devices. This paper summarizes the real-time systems and diagnostics developed by the Portuguese Fusion Euratom Association based on digital signal processors and field programmable gate arrays. © 2006 American Institute of Physics [ABSTRACT FROM AUTHOR]

Being user friendly should be the main guidance, beside the self-understood high performance, in today’s instrumentation development. Here we identify three components of the user-friendly policy: the all-in-one concept, customization, and connectivity. All-in-one is the concept of unification of various building blocks and thus various functionalities in one product. The customization is enabled by the product’s reconfigurability that allows a product to grow and support new requirements and applications without changing hardware. The consequence of the two is the capacity of the single instrument to perform a variety of tasks that before were split among different devices. The last of the three is connectivity that improves the relationship between controls and beam diagnostics, brings out-of-the-crate freedom, and opens unforeseen possibilities for intra-accelerator cooperation and remote technical support. © 2004 American Institute of Physics [ABSTRACT FROM AUTHOR]