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The multi-terminal hybrid LCC/MMC HVDC has been applied to overcome the simultaneous commutation failure problem caused by the multi-infeed LCC-HVDCs in the East China. The high-speed and selectivity line protection method is required for the multi-terminal hybrid HVDC system. In this paper, the reflection and refraction of the fault traveling waves at different kinds of line terminals are characterized by transfer functions. Then the fault voltage as well as its first peak time at different line terminals when different internal and external faults occur are derived respectively. The conclusion proves that the first peak time of line-mode fault component voltage (FPTV) for internal faults is smaller than that for external faults, which is independent of fault impedance and fault type as well. Therefore, a FPTV-based non-unit ultra-high-speed dc line protection method is proposed. The algorithm is implemented in the developed protection prototype and validated in the Kun-Liu-Long three-terminal hybrid HVDC RTDS test system. The test results show that the proposed method can fast and correctly identify line faults in the multi-terminal hybrid HVDC system, even with 500 Ω fault impedance. Comparing with the traveling wave protection method of ABB, the proposed method improves the sensitivity when high-impedance faults occur. [ABSTRACT FROM AUTHOR]

Robust look-ahead dispatch (RLAD) is essential to manage uncertainties in power systems. As its key step, the worst-case scenario identification (WCSI) problem is cast to a max-min program. This computationally intensive procedure has to be performed repeatedly, impairing the computational efficiency of RLAD. To address this issue, an efficient RLAD scheme incorporating critical region preparation in gap time is proposed. The computation burden is mostly transferred from the online decision stage to the gap time via a customized technique based on multi-parametric programming. The accuracy of computing the critical regions is validated by the test in a six-bus system, and the proposed method is shown to cut down 21% of total iterations and save computational time dramatically by the test in a practical-scale system in Northeastern China. [ABSTRACT FROM AUTHOR]

The Jiangmen Underground Neutrino Observatory (JUNO) is a medium-baseline neutrino experiment under construction in China, with the goal to determine the neutrino mass hierarchy. The JUNO electronics readout system consists of an underwater front-end electronics system and an outside-water back-end electronics system. These two parts are connected by 100-m Ethernet cables and power cables. The back-end card (BEC) is the part of the JUNO electronics readout system used to link the underwater boxes to the trigger system and transmit the system clock and triggered signals. Each BEC is connected to 48 underwater boxes, and in total around 150 BECs are needed. It is essential to verify the physical layer links of the BEC before applying a real connection with the underwater system. Therefore, our goal is to build an automatic test system to check the physical link performance. The test system is based on a custom-designed field-programmable gate array (FPGA) board. In order to make the design general, only joint test action group (JTAG) is used as the interface to the PC. The system can generate and check different data patterns at different speeds for 96 channels simultaneously. The test results of 1024 continuously clock cycles are automatically uploaded to PC periodically. We describe the setup of the automatic test system of the BEC and present the latest test results. [ABSTRACT FROM AUTHOR]