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A flexible architecture is proposed in this paper for implementation Discrete Wavelet Transform (DWT) of 5/3 filter. The proposed architecture includes transforms modules, a RAM and bus interfaces. This architecture works in non separable fashion using a serial-parallel filter with distributed control to compute all the DWT (1D-DWT and 2D-DWT) resolution levels. The so-called lifting scheme represents the fastest implementation of the DWT. A VHDL model was described and synthesized using implementation of our architecture. Synthesis results show that Xilinx XCV600E FPGA implementation can be achieved with a frequency of about 108 Mhz, allowing processing rate between 85 and 187 frames per second for a range of standard picture dimensions. Speed/Area resulting from this processor is analyzed and is shown to demonstrate that our design achieves favourable performances with other FPGA based implementations. [ABSTRACT FROM AUTHOR]

There are a variety of applications areas that take advantage of the availability of three-dimensional data sets. These objects are represented as complex polygonal surfaces formed by hundreds of thousands of polygons, which causes a significant increase in the cost of storage, transmission and visualisation. Such models are usually not only geometrically complex, but they may also have various surface properties such as colour, textures and temperature, etc. This paper presents a extension of lifting scheme for the multiresolution decomposition and reconstruction of irregular triangle surface meshes with additional attributes. [ABSTRACT FROM AUTHOR]

The richness of wavelet transform has been known in many fields. There exist different classes of wavelet filters that can be used depending on the application. In this chapter, we propose a general purpose lifting-based wavelet processor that can perform various forward and inverse DWTs. Our architecture is based on M processing elements (PEs) that can perform either prediction or update on a continuous data stream in every clock cycle. We also consider the normalization step that takes place at the end of the forward DWT or at the beginning of the inverse DWT. To cope with different wavelet filters and different applications, we feature a multi-context configuration to select among various DWTs and an arbitrary memory size to compute the transform. For the 16-bit implementation, the estimated area of the proposed wavelet processor with 8 PEs and 2x512 words memory in a 0.18-μm technology is 2.3 mm square and the estimated frequency is 347 MHz. [ABSTRACT FROM AUTHOR]

In this paper, a new approach for designing and implementing lifting-based VLSI architectures for two-dimensional discrete wavelet transform (2-D DWT) is introduced. As a result, two high performance VLSI architectures that perform 2-D DWT for lossless 5/3 and lossy 9/7 filters are proposed. In addition, the architectures implement symmetric extension for boundary treatment. First, two pipelined architectures consisting of two stages, the row and column processors stages, were developed for 5/3 and 9/7 filters. The internal memory between the row and the column processors is reduced to a few registers. Second, in order to speedup the computation, fully pipelined datapath architectures for row and column processors were separately developed for each 5/3 and 9/7 filters that can be incorporated into the two architectures developed in the first part. Finally, 100% hardware utilization is achieved. [ABSTRACT FROM AUTHOR]