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2. FAST AND POWER-EFFICIENT CMOS SUBRANGING ADCs.

Author

Van Roermund, Arthur H. M., Casier, Herman, Steyaert, Michiel, Van Der Goes, F. M. L., Mulder, J., Ward, C. M., Lin, C.-H., Kruse, D., Westra, J. R., Lugthart, M., Arslan, E., Bajdechi, O., Van De Plassche, R. J., and Bult, K.

Abstract

This paper presents a two-step subranging ADC architecture based on interpolation, averaging, offset compensation and pipelining techniques. Application of these techniques results in fast and power-efficient converters with an accuracy between 8b and 12b. [ABSTRACT FROM AUTHOR]

Published
2006
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