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68 results on '"Srikanthan P"'

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1. Efficient Techniques and Hardware Analysis for Mesh-Connected Processors.

2. Speculative Issue Logic.

3. Building a Terabit Router with XD Networks.

4. Implementation of a Hybrid TCP/IP Offload Engine Prototype.

5. Implementation and Analysis of TCP/IP Offload Engine and RDMA Transfer Mechanisms on an Embedded System.

6. Efficient VLSI Architectures for Convolution and Lifting Based 2-D Discrete Wavelet Transform.

7. A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures.

8. Area-Time Efficient Systolic Architecture for the DCT.

9. Targeted Data Prefetching.

10. Application-Specific Hardware-Driven Prefetching to Improve Data Cache Performance.

11. Cache Leakage Management for Multi-programming Workloads.

12. A Memory Bandwidth Effective Cache Store Miss Policy.

13. A Study on the Performance Evaluation of Forward Link in CDMA Mobile Communication Systems.

14. FPGA Implementation and Analyses of Cluster Maintenance Algorithms in Mobile Ad-Hoc Networks.

15. Analysis of Real-Time Communication System with Queuing Priority.

16. VLSI Performance Evaluation and Analysis of Systolic and Semisystolic Finite Field Multipliers.

17. Application of Real-Time Object-Oriented Modeling Technique for Real-Time Computer Control.

18. Comparing Low-Level Behavior of SPEC CPU and Java Workloads.

19. Covert Channel Analysis of the Password-Capability System.

20. Efficient Architectural Support for Secure Bus-Based Shared Memory Multiprocessor.

21. DRIL- A Flexible Architecture for Blowfish Encryption Using Dynamic Reconfiguration, Replication, Inner-Loop Pipelining, Loop Folding Techniques.

22. A Practical Test Scheduling Using Network-Based TAM in Network on Chip Architecture.

23. Increasing Embedding Probabilities of RPRPs in RIN Based BIST.

24. Exploring Design Space Using Transaction Level Models.

25. Minimizing Power in Hardware/Software Partitioning.

26. A Technique to Reduce Preemption Overhead in Real-Time Multiprocessor Task Scheduling.

27. Determining Optimal Grain Size for Efficient Vector Processing on SIMD Image Processing Architectures.

28. D3DPR: A Direct3D-Based Large-Scale Display Parallel Rendering System Architecture for Clusters.

29. A Real Coded Genetic Algorithm for Data Partitioning and Scheduling in Networks with Arbitrary Processor Release Time.

30. Irregular Redistribution Scheduling by Partitioning Messages.

31. The Star-Pyramid Graph: An Attractive Alternative to the Pyramid.

32. Extending Address Space of IP Networks with Hierarchical Addressing.

33. The Channel Assignment Algorithm on RP(k) Networks.

34. Matrix-Star Graphs: A New Interconnection Network Based on Matrix Operations.

35. Morphable Structures for Reconfigurable Instruction Set Processors.

36. FPGAs for Improved Energy Efficiency in Processor Based Systems.

37. Biological Sequence Analysis with Hidden Markov Models on an FPGA.

38. A Configuration System Architecture Supporting Bit-Stream Compression for FPGAs.

39. A Switch Wrapper Design for SNA On-Chip-Network.

40. Software-Oriented System-Level Simulation for Design Space Exploration of Reconfigurable Architectures.

41. Exploiting Thread-Level Speculative Parallelism with Software Value Prediction.

42. Arithmetic Data Value Speculation.

43. Using Decision Trees to Improve Program-Based and Profile-Based Static Branch Prediction.

44. Making Power-Efficient Data Value Predictions.

45. Designing a Concurrent Hardware Garbage Collector for Small Embedded Systems.

46. A Register Allocation Framework for Banked Register Files with Access Constraints.

47. An Integrated Partitioning and Scheduling Based Branch Decoupling.

48. Improving the Performance of GCC by Exploiting IA-64 Architectural Features.

49. Embedding of Cycles in the Faulty Hypercube.

50. A Fault-Tolerant Routing Strategy for Fibonacci-Class Cubes.

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