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A reduced uneven multi-hexagon-grid search algorithm for fast integer pel motion estimation in H.264/AVC is presented. The objective is to reduce the number of candidates for the block matching by predicting the likely area in which the minimum sum of absolute differences (SAD) can be taken. For this purpose, the proposed algorithm employs directionally partial hexagon search patterns utilizing the motion vectors computed in previous stages which supply the spatial correlation characteristics between adjacent macro blocks and the temporal ones between video frames. Experimental results show that the proposed method can save 39%~69% of computational complexity compared with the original one at the cost of negligible degradation on RD performance. [ABSTRACT FROM AUTHOR]

In this paper, we introduce a service framework using the VPW (Virtual Personal World) and its associated service conflict resolution algorithm based on the VPW. In this new service model, users can manage their own spaces that include all things to support their services. Previous service frameworks are focused on designing adaptive software applications by using heterogeneous devices and softwares. However, these service frameworks have some problems to provide adaptive services to the users. To resolve the limitation that is caused by multi-user environment, we propose a service conflict resolution algorithm. Therefore, our proposed service framework based on the VPW can support more user-centric services, reduce the number of service conflicts, and improve the number of conflict resolutions. The experiment result shows that almost 40% resolution rate can be achieved comparing with the location based system and 30% work time can be improved comparing with the location based system. [ABSTRACT FROM AUTHOR]

Today's portable electric consumer devices tend to include more multimedia processing capabilities. This trend results increased processing resources, thus causing more power consumption. Therefore, the power-efficiency becomes important due to battery operated nature of portable devices. In this paper, we propose a reconfigurable data cache architecture, in which data allocation to a cache is constrained by address range configuration. Then we evaluate trade-off between performance and power efficiency. Comparing to the conventional cache architectures, power consumption can be reduced decently while maintaining miss rate of the proposed data cache similar to those of the conventional caches. The result shows that the reconfigurable data cache operates with 33.2%, 53.3%, and 70.4% less power when compared with direct-mapped, 2-way, and 4-way set-associative caches respectively. Keywords: low-power, cache architecture, embedded system, multimedia application. [ABSTRACT FROM AUTHOR]

This paper presents our experience in developing an embedded processor core model for an SOC design. We developed an ARM1136 processor simulation environment based on the ARM's MaxCore tool and the SimpleScaclar simulator. A MaxCore ARM1136 instruction accurate (IA) model is developed to support application programmers for the writing application programs from the early design stage. The MaxCore ARM1136 processor model supports all ARMv4, ARMv5TE and ARM v6 instruction sets with 418 LISA instructions. This MaxCore IA Model can be integrated with the ARM's MaxSim system level design environment to develop application softwares and perform architecture explorations. A SimpleScalar ARM1136 cycle accurate (CA) model is also developed by enhancing the existing SimpleScalar-ARM version in the SimpleScalar 3.0. Most important micro-architectural features of ARM1136 processor are implemented in the enhanced SimpleScalar simulator. The accuracy of the developed SimpleScalar-ARM 1136 simulator is about 97% compared to ARM 1136 RTL simulation with the Dhrystone benchmark (100 iterations). [ABSTRACT FROM AUTHOR]

Despite the importance of seamless connectivity in ubiquitous computing, research for seamless connectivity has not been considered properly. To provide seamless connectivity, this paper proposes an application execution model for seamless services with an intelligent context-aware handoff scheme based on context information, such as user intentions and application requirements as well as issues of network layer. In this paper, we define several profiles reflecting various context informations and design basic modules organizing middleware architecture for seamless service management and efficient vertical handoff (VHO) management. Consequently, the proposed seamless service management with context-aware handoff scheme provides service continuity in ubiquitous computing environment by preventing unnecessary handoffs, changing application service modes adaptively, and eventually maintaining optimal network configuration. And also simulation results show about 38% enhanced performance in the processing rate, about 13% enhanced performance from service continuity, and about 29% enhanced performance in the processing time, compared with conventional schemes. [ABSTRACT FROM AUTHOR]

Specifically ubiquitous computing paradigm is based on seamless connectivity. And also to guarantee the seamless connectivity, an intelligent network management between heterogeneous network interfaces, called vertical handoff (VHO), should be designed. Besides, conventional VHO schemes are based on network information only, and do not provide any service manage-ment scheme for seamless service. For this reason, this paper proposes a middleware architecture supporting efficient seamless connectivity with service management. In this architecture, we define modules to perform VHOs in accordance with contexts of services, user intention as well as network information. And also we define profiles used to express the contexts related to the process of VHOs and service management. With the proposed scheme, we can reduce the number of unnecessary VHOs and application failures significantly. This leads to around 130% of enhancement in data throughput, and also 85% of application failures can be reduced. Keywords: Vertical handoff, seamless connectivity, application profile, context-aware processing, and ubiquitous computing. [ABSTRACT FROM AUTHOR]

Power-aware design is one of the most important areas to be emphasized in multimedia mobile systems, in which data transfers dominate the power consumption. In this paper, we propose a new architecture for motion compensation (MC) of H.264/AVC with power reduction by decreasing the data transfers. For this purpose, a reconfigurable microarchitecture based on data type is proposed for interpolation and it is mapped onto the dedicated motion compensation IP (intellectual property) effectively without sacrificing the performance or the system latency. The original quarter-pel interpolation equation that consists of one or two half-pel interpolations and one averaging operation is designed to have different execution control modes, which result in decreasing memory accesses greatly and maintaining the system efficiency. The simulation result shows that the proposed method could reduce up to 87% of power caused by data transfers over the conventional method in MC module. Keyword: H.264/AVC, motion compensation, quarter-pel interpolation, low-power, memory access, multimedia SoC, system architecture. [ABSTRACT FROM AUTHOR]

Context-awareness is one of the most important technologies for the ubiquitous computing. To embed such a technology into applications, first of all, a well-defined architectural framework is required to support applications to obtain necessary contexts. Several studies have been proposed, but most of them overlooked one fundamental feature that contexts are subjective things and context-awareness is subjective behavior. Thus, providing pre-defined, pre-programmed operators which generate contexts by combining a couple of sensed data is very impractical. Instead, in this paper, we provide a well-defined programmable interface to applications, so that they can obtain and use contexts according to their own ideas. To evaluate our architecture and context interface, we implement all components comprising of the context infrastructure and perform several experiments. The results show the proposed method provides a flexible and expressive interface, but does not countervail the performance. [ABSTRACT FROM AUTHOR]

Service broker is a software component that maps user's request to proper services. By using the broker, users can access various services without any knowledge of the services. However, design of the service broker for GCE (Global Computing Environment) is quite difficult because a broker cannot cope with all the information of services which are spread over the world. Thus, we need to build new architectural foundations for global service brokering. In this paper, we propose a scalable broker system for GCE based on the federation of personalized brokers. In our broker system, every user can have a service broker. The broker maintains the information of services related to the user and exchanges the information with neighboring brokers if necessary. As a result, the broker can provide proper services to users faster and a burden of brokers can also be decreased. Experimental results show that the proposed service broker can reduce the average service discovery time and the average operation overhead of each broker comparing to other brokering architectures. [ABSTRACT FROM AUTHOR]

An effective matrix operation is critical to process 2-D DCT. This paper presents a hierarchically controlled SIMD array (HCSA) well suited to matrix computations, in which a conventional 2-D torus is enhanced with the hierarchical organization of control units and the global data buses running across the rows and columns. The distinguished features of the HCSA are the diagonally indexed concurrent broadcast and the efficient data exchanges among PEs through either row or column broadcast. Therefore, the HCSA can provide significant improvement on computation steps of DCT. For the performance evaluation, an algorithmic mapping method is used and the number of computation steps is analytically compared with semisystolic architecture. [ABSTRACT FROM AUTHOR]

In order to alleviate the ever-increasing processor-memory performance gap of high-end parallel computers, on-chip compressed caches have been developed that can reduce the cache miss count and off-chip memory traffic by storing and transferring cache lines in a compressed form. However, we observed that their performance gain is often limited due to their use of the coarse-grained compressed cache line management which incurs internally fragmented space. In this paper, we present the fine-grained compressed cache line management which addresses the fragmentation problem, while avoiding an increase in the metadata size such as tag field and VM page table. Based on the SimpleScalar simulator with the SPEC benchmark suite, we show that over an existing compressed cache system the proposed cache organization can reduce the memory traffic by 15%, as it delivers compressed cache lines in a fine-grained way, and the cache miss count by 23%, as it stores up to three compressed cache lines in a physical cache line. Keywords: Parallel processing, processor-memory performance gap, on-chip compressed cache, fine-grained management, internal fragmentation problem. [ABSTRACT FROM AUTHOR]