Search

Shadow elimination is required especially when processing images captured outdoors for object recognition. Whereas room lights make diffuse shadows, the sunlight makes strong shadows leading to misrecognition of objects or some patterns such as humans or traffic signs. To remove this harmful effect of shadows on image processing, we developed a simple algorithm mimicking a human psychological characteristic about shadow detection. [ABSTRACT FROM AUTHOR]

In this article we present a system for secure human-machine interaction. User verification is done based on face matching, and commands to machine are delivered by arm gesture. Algorithms used in our system for face matching and arm posture detection get some inspiration from brain visual functions and architecture. Higher complexity modules are implemented in hardware to achieve higher computational efficiency needed for real time processing. [ABSTRACT FROM AUTHOR]

In this paper, we propose an FPGA-based collision warning system for advanced automobile driver assistance systems or autonomous moving robots. The system consists of three function blocks: edge detection, moving-object detection and danger evaluation and collision warning. In the moving-object detection, the system uses a moving-object detection algorithm inspired by neuronal propagation in the hippocampus, which can run in high speed and low calculation cost. We have applied the system in a robot. It can detect moving objects with a speed range of 3-47cm/s with a sampling period of 33ms for an input image of 320×240 pixels, and can output a warning against dangerous regions in the input image. [ABSTRACT FROM AUTHOR]

The hierarchical convolutional neural network models are considered promising for robust object detection/recognition. These models require huge computational power for performing a large number of multiply-and-accumulation (MAC) operations. In this paper, first we discuss efficient calculation schemes suitable for 2D MAC operations. Then we review the related algorithms and LSI architecture proposed in our previous work, in which we use a projection-field-type network architecture with sorting of neuron outputs by magnitude. For the LSI implementation, we adopt a merged/mixed analog-digital circuit approach using a large number of analog or pulse modulation circuits. We demonstrate the validity of our LSI architecture by testing proof-of-concept LSIs. It is essential to develop efficient and parallel A/D and D/A conversion circuits in order to connect a lot of on-chip analog circuits with the external digital system. In this paper, we also propose such an A/D conversion circuit scheme. [ABSTRACT FROM AUTHOR]

Hierarchical convolutional neural networks are a well-known robust image-recognition model. In order to apply this model to robot vision or various intelligent real-time vision systems, its VLSI implementation is essential. This paper proposes a new algorithm for reducing multiply-and-accumulation operation by sorting neuron outputs by magnitude. We also propose a VLSI architecture based on this algorithm. We have designed and fabricated a sorting LSI by using a 0.35 μm CMOS process. We have verified successful sorting operations at 100 MHz clock cycle by circuit simulation. [ABSTRACT FROM AUTHOR]