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This paper studies the different power-performance trade-offs at architectural and block level to come to the most energy-efficient UWB system for operation in the 0-960MHz frequency band. This is achieved by designing for the lowest energy per useful received bit. Different receiver architectures are explored and compared against each other. After the selection of the most optimal architecture, the trade-offs inside the different analog building blocks of this receiver are studied. Our results show that the most energy-efficient solution makes use of a complex analog correlation UWB receiver, with an LNA with a Pin,1dBc back-off of -5dB, 3-bit ADC's and a 500MHz QVCO. The requirements for the ADC offset, QVCO phase noise and mixer linearity are rather relaxed, which enables a low-power implementation. [ABSTRACT FROM AUTHOR]