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In order to reduce the manufacturing cost for future 60 GHz products, a high integration level is necessary. Recent results on mHEMT and pHEMT multifunctional receiver/transmitters utilizing are reported. The building blocks for highly integrated millimeterwave front-end circuits based on III-V-technologies such as mixers, amplifiers, frequency multipliers, and VCOs are presented in this work. Balanced and single ended 7-28 GHz MMIC frequency multipliers are described and compared. Multifunctional MMICs utilizing single ended, subharmonically pumped, balanced and single sideband mixers are reported. Examples of multi-stage mHEMT and pHEMT wideband amplifier for example covering 43-64 GHz with a gain of 24 dB, a minimum noise figure of 2.5 dB and ripple of 2 dB are shown. [ABSTRACT FROM AUTHOR]

Implicit in the design of a 60GHz receiver front-end is the re- quirement for broadband amplification and gain flatness in order to support advanced modulation schemes. As we have seen from lower frequency wireless systems, the choice of technology often dictates the system architecture. While either silicon CMOS or silicon Bipolar technology could be used for implementation, cost, availability, performance and time to market constraints typically dictate the technology choice. The trade-offs between CMOS and Bipolar/BiCMOS technologies for mm-wave receiver circuits are outlined in this paper. Realizing low-noise performance and gain flatness over a wide bandwidth is used as a case study from both the circuit and system points of view. [ABSTRACT FROM AUTHOR]

This paper examines the suitability of advanced SiGe BiCMOS and sub 65nm CMOS technologies for applications beyond 80GHz. System architectures are discussed along with the detailed comparison of VCOs, LNAs, PAs and static frequency dividers fabricated in CMOS and SiGe BiCMOS, as required for automotive cruise-control radar, high data-rate radio, and active and passive imaging in the 80GHz to 160GHz range. It is demonstrated experimentally that prototype SiGe HBT and BiCMOS technologies have adequate performance for all critical 80GHz building blocks, even at temperatures as high as 125 C. Although showing promise, existing 90nm GP CMOS and 65nm LP CMOS circuits at these frequencies remain significantly inferior to their SiGe counterparts. [ABSTRACT FROM AUTHOR]

An overview of analog and RF design concepts in silicon process technologies is presented, with the focus on high-power applications at mmWave frequencies and above. Key power amplifier design tradeoffs and high-frequency trends will be given. This includes power amplifier circuit design and packaging examples at 60 GHz. [ABSTRACT FROM AUTHOR]

In this work, new receiver concepts and key building blocks, at circuit level, for future millimeter-wave wireless communications standards are introduced. Starting from passive and active devices, trade-offs between technology, performance and circuit choices of millimeter-wave RF front-end circuits are discussed. In particular, power consumption, noise and linearity trade-offs in low-noise amplifiers, mixers, frequency dividers and oscillators are considered. The concepts derived are applied to a large class of wireless communications standards that are broadband in nature at RF and/or require a broadband IF. [ABSTRACT FROM AUTHOR]

The large scale deployment of the voice over IP, or voice over packet technology and the migration of this technology towards the edge of the network stimulates a revival of SLIC and CODEC design. The basics of this existing technology are refreshed and the architecture of a specific implementation is described in this paper. New smart power technologies with single chip low voltage CMOS and high voltage DMOS and bipolar devices allow for full single chip SLIC & CODEC integration. Another option is to put the low voltage CODEC in a deep sub micron system on chip with a mini-SLIC, integrating only the high voltage drivers. In the field new voice circuits get deployed now to bring voice to the phone over the wideband network and do the conversion from wideband IP coded voice to the analogue real world speech signals as close to the phone as possible via an Analogue Telephone Adaptor [ATA]. The conversion can be done in the phone as a real IP-phone, in a PC (Skype) via the audio of the PC or via an ATA, driving a regular phone. The conversion can also be done in the house via a VoIP to POTS converter next to the wideband modem, in your garage e.g. to drive your existing home phone cabling. The conversion can also be done with an ATA in the street cabinets driving only the last kilometer to your home phone. In this paper a Short Haul Line Integrated Circuit [SHLIC] is described, used to transmit Voice over Internet Protocol, also called VoIP, IP Telephony, Internet telephony, wideband telephony, wideband phone, and the routing of voice conversations over the Internet or through any other IP-based network. The SHLIC is a pure analogue circuit processed in a high voltage technology. Also the CODEC, performing the wideband 16Ksamples/s or A/µ law narrow band signal processing, is briefly described. [ABSTRACT FROM AUTHOR]

This paper discusses very high frequency radio links from the application level down to the circuit constraints. Because of the technical difficulties and higher cost of technologies and packaging, applications at these frequencies only make sense when the special properties of these high frequencies are offering clear advantages for these applications. Such advantages can be higher system capacity, better security and privacy, or higher spatial resolution. Exploiting these advantages requires careful choices in system design and architecture, and imposes specific constraints on circuits and technologies. In most cases, it will also require beam forming through phased array antenna structures. Implementation of the signal processing for beam forming can be achieved in an efficient way in the RF domain. [ABSTRACT FROM AUTHOR]

New and improved xDSL standards are developed to bridge the last mile between the Central Office (CO) and the end user. The aDSL2+ standard doubles the bandwidth of a basic aDSL system to 2.2MHz and hence increases the bitrate up to 24Mb/s. The high Crest Factor (CF) of Discrete Multi Tone (DMT) modulated signals, however, poses serious problems on an efficient and low cost implementation of the line driver in the CO [1]. With the emerging nanometer technologies the line driver remains more than ever the bottleneck for lowering the cost and power. The low supply voltages originating from nanometer technologies increase the current density in the line driver, which affects its efficiency and reliability. This paper presents a high voltage high efficient aDSL2+ CO line driver in a mainstream nanometer CMOS technology. [ABSTRACT FROM AUTHOR]

This paper presents a power-efficient high-speed serial interface solution, which is targeted for use in battery-operated mobile or handheld devices. Both transceiver topology and signaling protocol are described. High-speed differential and CMOS signaling are merged on the same wires. The signaling scheme contains link power management features and provides multiple communication modes to adapt efficiently to bandwidth needs. This interface has been implemented in 65nm CMOS and measurement results are shown. [ABSTRACT FROM AUTHOR]

To overcome the limitations of traditional linear amplifiers: a reduced efficiency when operated with amplitude modulated signals, a switched linearization technique is presented. This technique is analog to the linear amplification by a class D-amplifier at baseband. By pulse-width modulation of the signal envelope, the class-D operation is extended towards RF systems too. The spurious emissions generated by the switching operation, are well separated from the signal band by the use of an asynchronous pulse-width modulator. Measurements on a test-chip prove the feasibility of the switching technique. [ABSTRACT FROM AUTHOR]

This paper gives an overview of several design issues for CMOS Power Amplifiers (PA) for wireless and mobile communications. The challenges, faced by the RF PA designer, and the different trade-offs, encountered during the design process, are clearly indicated. The idea of power combining is introduced and it is clarified how this technique can alleviate some of the problems related to the aggressive CMOS scaling. The theory is clarified by several design examples that cover a frequency range from the lower GHz as high as 60 GHz. [ABSTRACT FROM AUTHOR]

In this paper we will explain the trends in short-range broadband communication and investigate the technology requirements necessary for implementing the PA building block. Further we will discuss the importance of the power grid on the stability of the PA. Finally a single-ended integrated PA, part of a WiMedia/MBOA compliant UWB transceiver, is presented. [ABSTRACT FROM AUTHOR]

In automotive power applications protection and diagnosis is getting more and more important. Main reasons for this trend are safety requirements, high reliability and complex power management of modules in a car. This paper describes aspects and challenges of designing smart power high-side switches embedded in automotive systems to drive inductive, capacitive and resistive loads. [ABSTRACT FROM AUTHOR]

We present a CMOS single-chip electronic compass sensor including the complete digital signal processing for accurate heading calculation, which is the continuation of a work presented at the International Solid State Circuits Conference (ISSCC) 2007 in San Francisco/USA [1]. The device's analog part consists of Hall based three-axis magnetic field transducer with integrated magnetic concentrator that operates as passive magnetic amplifier. The analog amplification chain features a gain of up to 20'000. A true-12-bit extended counting ADC converts the amplified magnetic field signals into the digital domain where a 16-Bit microcontroller calculates the heading information and outputs it via an SPI interface. The compass sensor is realized in 0.35um low voltage CMOS technology plus a simple batch processing step for deposition of a metal layer. The compact die size of 2.3 mm × 2.8 mm allows for packaging into a standard 4mm × 5mm × 1mm surface mount plastic package. The heading resolution is better than 0.5 degrees and the accuracy better than +/-2 degrees. [ABSTRACT FROM AUTHOR]

A principle and realization of an ASIC for a fast, precise, and high resolution Contact-less Inductive Position Sensor (CIPOS), is described. The inductive contact-less sensor is suitable for angular or linear position sensing. Advantage of used measurement principle is, that it is strictly ratio metric independent of absolute values. The mechanical robustness, insensitivity to temperature variation, electrical or magnetic fields as well as its mechanical tolerances make the sensor ideal for harsh automotive environment. The sensor fulfils all the requirements for safety relevant applications. The presented ASIC includes sensor excitation, precise input signal analog and digital processing as well as the output signal transmitter. The signal path and main blocks are described. [ABSTRACT FROM AUTHOR]

Eye-RIS is the name of a family of vision systems which are conceived for single-chip integration using CMOS technologies. The Eye-RIS systems employ a bio-inspired architecture where image acquisition and processing are truly intermingled and the processing itself is realized in two steps. At the first step processing is fully parallel owing to the concourse of dedicated circuit structures which are integrated close to the sensors. These circuit structures handle basically analog information. At the second step, processing is realized on digitally-coded information data by means of digital processors. Overall, the processing architecture resembles that of natural vision systems, where parallel processing is made at the retina (first layer) and significant reduction of the information happens as the signal travels from the retina up to the visual cortex. This chapter outlines the concept of the Eye-RIS system and its main components and presents experimental data to illustrate its practical operation. [ABSTRACT FROM AUTHOR]

Applications using rf radios operating at frequencies above 1 GHz are proliferating. The highest operating frequencies continue to increase and applications above 10 GHz and up to 77 GHz are already emerging. Systems become more complex and devices need to operate at several different frequency bands using different wireless standards. The rf-front end sections of these devices are characterized by a high diversity of components, in particular high precision passive components. In order to be produced cost-effectively, these elements need to be integrated along with the semiconductor devices. This paper describes the requirements for successful integration of rf-passive devices and proposes multilayer thin film technology as an effective rf-integration technology. [ABSTRACT FROM AUTHOR]

In this paper we want to review the development of pipelined and SAR ADCs from basic concepts to novel techniques. We will demonstrate that there are quite a lot of similarities and that there are a few major discrepancies. Based on this we draw comparisons and point out specific strengths and weaknesses of the individual architectures. [ABSTRACT FROM AUTHOR]

This paper examines system and circuit design techniques for a micro-Watt node operating at a power level low enough to enable the use of an energy scavenging source. Despite several architectures have been investigated in order to reduce the overall system power consumption, none of them is able to guarantee robustness of the link and ultra-low power consumption at the same time. A survey of the most advanced architectures meant for ultra-low power transceivers is described. Advantages and drawbacks of all these systems are discussed and the reasons for an architecture based on Frequency-Hopping (FH) Spread-Spectrum (SS) are discussed. Finally a novel FH synthesizer based on a digital pre-distortion architecture is proposed in order to reduce the power consumption of the hopping synthesizer. The FH architecture together with a frequency offset robust demodulation technique allows a reduction by a factor 8 of the power consumption compared to the state-of-the-art synthesizers. Furthermore, a single RF block front-end is obtained combining the VCO and the PA. The novel RF front-end can be directly coupled to the antenna through a balun and the system is able to deliver -18 dBm output power on a 50 Ω load at 1 mA current consumption (2 V power supply). To prove the new synthesizer principle a communication link in the 902-928 MHz ISM band has been set-up. The receiver, mainly software with a flexible RF frontend, adopted a ST-DFT demodulation algorithm and achieved a BER smaller than 1.1% at -25 dBm output power, with TX and RX antennas placed at 8 meters distance in a NLOS condition and in a common office environment. [ABSTRACT FROM AUTHOR]

Autonomy and size are the most important challenges faced when designing radios for distributed wireless sensor networks (WSN). Reducing power consumption requires optimization across all the layers of the communication stack. The WSN platform developed at CSEM therefore uses a co-design approach that combines WiseMAC, a low-power media access control protocol, with the WiseNET SoC, a complex system-on-chip sensor node to exploit the intimate relationship between the MAC-layer and the radio transceiver parameters. This paper reviews the design and realization of the WiseNET SoC featuring a low-power 1V short-range UHF radio transceiver implemented on a 0.18μm standard digital CMOS process. The WiseNET radio consumes only 2.3mW in receive mode with a sensitivity smaller than -108-dBm at a BER of 10-3 for 25kb/s FSK in the 433MHz ISM band. The design, simulation and validation of the WiseMAC protocol are also detailed in the context of the deployment of a small ad-hoc network experiment at CSEM, demonstrating that the consumption of the WiseNET solution is more than an order of magnitude lower than a comparable Zigbee-based solution. [ABSTRACT FROM AUTHOR]

The number of available electronic implantable devices is increasing every year. The complexity and functionality of these devices is also increasing at a significant rate. Communications with these complex devices for physician adjustment and to collect data is becoming increasingly important to provide the maximum patient comfort and the most effective treatment for medical conditions. A Communications band has been allocated in both North American and Europe specifically for communications with implanted devices. This paper reviews some of the unique requirements for an implanted wireless transceiver, regulatory requirements of the Medical Implantable Communication Service (MICS) band, provides a description of a product competing in this arena and a unique crystal startup circuit that can significantly reduce power consumption in power critical implant applications. [ABSTRACT FROM AUTHOR]

This paper studies the different power-performance trade-offs at architectural and block level to come to the most energy-efficient UWB system for operation in the 0-960MHz frequency band. This is achieved by designing for the lowest energy per useful received bit. Different receiver architectures are explored and compared against each other. After the selection of the most optimal architecture, the trade-offs inside the different analog building blocks of this receiver are studied. Our results show that the most energy-efficient solution makes use of a complex analog correlation UWB receiver, with an LNA with a Pin,1dBc back-off of -5dB, 3-bit ADC's and a 500MHz QVCO. The requirements for the ADC offset, QVCO phase noise and mixer linearity are rather relaxed, which enables a low-power implementation. [ABSTRACT FROM AUTHOR]

This work describes ongoing research into system architectures, circuit design techniques, and new technologies applicable to low power wireless sensing. We will present completed proof-of-concept research as well as propose ideas for future architectures. It is shown that MEMS-based transceiver blocks in combination with a dedicated carrier sense receiver can substantially reduce the communications energy of a sensor network. Additionally, novel methods for power regulation and modular packaging will be introduced. [ABSTRACT FROM AUTHOR]

The governing body in the United States, the Federal Communications Commission (FCC), has issued ultra-wideband regulations, under Part15 of the Commission's rules on April 22, 2002. Therefore, ultrawideband transmissions (intentional emissions) under certain frequency and power limitations have been permitted. The US has openly endorsed UWB based consumer products. Ultra-wideband offers significant contributions and advantages but simultaneously a number of challenges also need to be addressed. One of the key challenges is the co-design of an impulse generator and miniaturized antennas for ultra-wideband impulse radio. This has been designed and fabricated in 0.18μm CMOS technology. Measurements show the correct operation of the circuit for supply voltages of 1.8V and a power consumption of 45mW. The output pulse approximates a Gaussian monocycle having a pulse duration of about 375ps. Proper modulation of the pulse in time is confirmed [1]. In addition, to meet the stringent FCC stipulated frequency spectrum, an orthonormal [2] ladder filter with a Daubechies' impulse response is employed. The filter is implemented using novel 2-stage gm-C cells employing negative feedback. Simulation results in CMOS 0.13μm technology show that this pulse generator requires a total current of 30mA at a 1.2V power supply. The frequency coverage of the simulated waveform is about 85% of the FCC mask. [ABSTRACT FROM AUTHOR]

Modelling of ICs is mostly "just" restricted to the functional behavior of the design. Extending the modelling requirements into the EMC domain, including signal and power integrity and incorporating the application with the measurement environment requires a different approach. Fortunately, the IC in its package has only a limited number of pins/balls to the PCB connected thereto. A new approach is given which is presently under discussion and development in international standardization (IEC62433-x) by IEC SC47A/WG2, but also by other bodies like: EIA,IEEE [10, 12, 15] and/or proprietly organizations. [ABSTRACT FROM AUTHOR]

This paper presents a structured methodology that, despite it is not conclusive for all cases, can support a design engineer to develop and/or debug electronic circuits for electromagnetic susceptibility (EMS). This methodology is well suited to investigate continuous time analog electronic systems, modules or circuits and does not require any special tools. The method is flexible, can be applied in many cases by simple reasoning and is customizable towards specific needs. [ABSTRACT FROM AUTHOR]

The design of integrated circuits for automotive applications has to meet challenging EMI requirements. In order to determine the cause of most common failures it is necessary to perform research in order to improve concept, design and layout of new or present products. In this article the concept/design analysis and results of fundamental blocks such as comparator/opamp, internal voltage supply and bandgap are presented. [ABSTRACT FROM AUTHOR]

This chapter deals with the effect of electromagnetic interference on the operation of analog front-end like operational amplifier and switched capacitor circuits. In particular, the offset, which is generated in the input differential stage of an operational amplifier is evaluated by an analytical model and a new circuit topology immune to RFI is proposed. Furthermore, the distortion of RFI in a basic switched capacitor circuit is analyzed and a new simple model for MOS switches is derived. Such a model is employed to predict RFI-induced upset in complex SC circuits. [ABSTRACT FROM AUTHOR]

Semiconductor companies face the demand for ‘first silicon success' to be competitive. Substrate current effects are one major cause for redesigns in junction-isolated Smart Power technologies and they put ‘first silicon success' at risk. Substrate currents are difficult to control because they are three-dimensional in nature and are strongly layout dependent. Moreover, protection measures show counteracting effects, and minority and majority carrier effects may occur at the same time. [ABSTRACT FROM AUTHOR]

Electromagnetic emission needs to be considered in the design flow of automotive ICs. Complex ICs require on one hand early forecasts and accurate sign-offs for EMI, on the other hand their EMI modeling and simulation is very complex. Approaches and solutions are presented in this paper. [ABSTRACT FROM AUTHOR]

In this paper a new mode of operation for Sigma-Delta Modulation (SDM) is proposed and applied to AD conversion. The proposed operation is identified as a sub-harmonic limit-cycle mode. It is shown, that in such sub-harmonic mode a more aggressive loop filter function can be applied that results in a better modulator performance. Moreover, most of the building blocks in the SDM loop operate at a frequency that is an integer fraction of the applied sampling frequency. That brings several very attractive advantages: a reduction of the required power consumption per converted bandwidth, immunity to excessive loop delays and to DAC waveform asymmetry, and a higher tolerance to clock imperfections. The proposed SDM ADC offers an alternative to low-speed low-performance low-cost and high-speed high-performance and high-cost implementations by introducing a new trade-off between limit cycle frequency and clock frequency. [ABSTRACT FROM AUTHOR]

This paper describes how offset calibration can be used to enhance the speed-resolution performance of ADCs while maintaining low levels of power dissipation. After selecting a high-speed ADC topology, we will justify the need for offset calibration and then present a brief overview of different ADC calibration topologies, indicating their relative merits and drawbacks. We will then describe in more detail how one-time foreground calibration was used to achieve a 0.18 μm CMOS, 1.8V, 1.6GS/s, 8b folding-interpolating ADC with 7.26 ENOB at Nyquist, which only dissipates 774 mW. [ABSTRACT FROM AUTHOR]

This paper presents a two-step subranging ADC architecture based on interpolation, averaging, offset compensation and pipelining techniques. Application of these techniques results in fast and power-efficient converters with an accuracy between 8b and 12b. [ABSTRACT FROM AUTHOR]

Architectures for ADCs at 1 Gigasample/second (1 GSa/s) and beyond now include flash, folding and interpolating as well as the time interleaving of slower unit converters such as pipeline and even successive approximation ADCs. In addition, CMOS is taking over in this former bastion of bipolar technology. We describe the issues common to all architectures: bandwidth, power, I/O, data storage, and cost. We examine these issues in detail for the time-interleaved approach as exemplified by two 8-bit ADCs operating at 4 GSa/s and 20 GSa/s, implemented in CMOS. [ABSTRACT FROM AUTHOR]

Implementation options for very high speed ADCs are discussed by first reviewing performance limiting mechanisms then comparing the various architectures and building blocks typically used in these converters. Results for a 5b 22GS/s ADC are presented. [ABSTRACT FROM AUTHOR]