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This paper presents an architectural study that may be used to design and develop a general, efficient hardware for multiconnected networks. Starting from the constraints, the proposed design flow allows an accurate evaluation of cost and performance of the final implementation. The generality of the architecture permits the realization of networks with practically any size or topologies. [Copyright &y& Elsevier]

This paper presents the experimental results of a research project financed by INFN (National Institute for Nuclear Physics). The goal of this project is to realize a cluster of personal computers (PCs) suitable for distributed software in the field of nuclear physics. The developed hardware must have a low cost and must be able to interconnect 32 PCs with an expansion capacity of up to 100. Due to the requirements of this research project, it seems natural to look at it as an application of our general hardware architecture presented in [Campobello et al., Hardware for Multiconnected Networks: The Design Flow]. Here, we present the results obtained and compare them with other works in literature. The results show that our architecture is preferable when low cost hardware and high performance are the goals. [Copyright &y& Elsevier]