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A true random number generator (TRNG) using Digital clock manager (DCM) blocks of a Xilinx FPGA has advantages of minimal usage of logic elements and tunability of clock frequencies to search for better randomness. Its operating principle is beat frequency detection, which uses the least significant bits (LSBs) of a counter that counts the number of successive logic-ones captured by a D flip-flop. In this brief, we evaluate the DCM-based TRNG with 100 frequency pairs. The findings of this brief include: 1) only 12 frequency pairs passed the diehard statistical tests when three LSBs were extracted as directed in the previous work; 2) the value of the counter exhibits biphasic histograms; 3) small counter values show less uncertainty; and 4) the number of frequency pairs that passed the tests was doubled to 24 by extracting only one LSB from small counter values, with a 16.9% reduction in the generation rate. [ABSTRACT FROM AUTHOR]

A multi-channel signal-conditioning and phase-detection concept is implemented in the prototype design using the high-precision OPAMP, high-speed comparators, high Q filters, high-density FPGA (Field Programmable Gate array), 10 MHz parallel-multiplying DACs (Digital to Analog Converter), etc. The complete digital-logic for the phase-detection is implemented inside the logic cells of FPGA using VHDL code, with high speed 100 MHz clock generated from Digital Clock Manager (DCM), which is used to measure the time elapsed between zero crossings of the two signals coming from reference and probe paths of the diagnostics. The logic is implemented to measure either leading or lagging phase and also to accumulate the total phase difference throughout the shot duration with the maximum value of accumulated phase of 5760 (16 cycles × 360°) degree and a resolution of 3.6 °. A precision high speed and high bandwidth (80 MHz) operational amplifiers are used as the front end-electronics component for conditioning the high-frequency (1 MHz) and low amplitude signal (μV). The hardware detail, implementation concept in FPGA and testing results will be presented in the paper. [ABSTRACT FROM AUTHOR]