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We propose a novel approximate computing technique for low-power ternary multiplication. A carry-truncated ternary multiplier, error compensation circuits, and $2 \times 2$ ternary multipliers with various accuracies are proposed using the low-power design methodology with carbon nanotube FETs. An accuracy-configurable design method is proposed to design energy-efficient $6 \times 6$ approximate ternary multipliers. The energy benefit of the proposed $6 \times 6$ approximate ternary multipliers have been verified using HSPICE simulation. The proposed approximate design shows 82.8% power-delay product with 41.8% mean absolute percentage error improvement over the previous approximate multiplier-based design. Image processing applications are conducted using the proposed approximate designs to confirm that the accuracy of ternary multiplication is satisfied the user’s requirement. [ABSTRACT FROM AUTHOR]

As technology moves toward the submicrometer regime, leakage current due to aggressive scaling and parameter variation has become a major problem in high-performance integrated circuit designs. Therefore, accurate measurement of the leakage current flowing through transistors has become a critical task for better understanding of process and design. In this brief, we propose a simple on-chip circuit technique for measuring a wide-range static standby (or leakage) current in a 65-nm technology with high accuracy. The circuit consists of a current amplifier, a bias stabilizer, and a voltage-controlled oscillator. The proposed leakage sensor is designed to measure leakage currents from 20 pA to 20 nA. Simulation results show that the proposed sensor has less than 8.4% error over a wide range of leakage currents (i.e., three orders of magnitude). Chip measurement results also indicate that the proposed leakage sensor is operating properly and measures the standby leakage current values of the devices under test within the possible range at different temperatures. The power consumption of the proposed leakage sensor was 0.6 mW when the leakage current was 1 nA, and the active area was 0.007 mm 2. [ABSTRACT FROM PUBLISHER]

Reducing a supply voltage in order to minimize power consumption in memory is a major design consideration in this field of study. In static random access memory (SRAM), optimum energy can be achieved by reducing the voltage near the threshold voltage level for near threshold voltage computing (NTC). However, lowering the operational voltage drastically degrades the stability of SRAM. Thus, in conventional 6T SRAM, it is almost impossible to read exact data, even when a small process variation occurs. To address this problem, an 8T SRAM structure is proposed which can be widely used for improving the read stability at lower voltage operation. In this paper, we investigate the channel length biasing effect on the read access transistor of the 8T SRAM in NTC and compare this with 6T SRAM. Read stability can be improved by suppressing the leakage current due to the longer channel length. Simulation results show that, in NTC, up to a 12× read-error reduction can be achieved by the 20 nm channel length biasing in the 8T SRAM compared to 6T SRAM. [ABSTRACT FROM AUTHOR]