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We live in a digital world surrounded by digital content in the form of images, videos, and much more which consume extensive power. With the extensive use of digital content in portable gadgets power consumption has been critical issue to act upon. The multiplier is the core component used in image processors and digital signal processors and by altering the properties of the multiplier system provides superior performance. In this work, we analyse the combined effect of the Self-Bias Transistor (SBT) Technique and Vedic multiplication algorithm on a multiplier unit realised using reduced transistor technique on conventional adders and CMOS array Multiplier units. Simulation results display the 76.5%, 80.15% and 84.21% drop in power consumption of 4-bit, 8-bit and 16-bit SBT based Vedic multiplier at 45 nm technology node respectively. The effectiveness of the proposed technique is also presented at 100 nm and 65 nm technology nodes. Further, the effect of the SBT-based Vedic multiplier on the delay and power-delay product is explored at 100 nm, 65 nm and 45 nm technology. It is found that SBT-based multipliers are power efficient on Gate Diffusion Input-based multipliers [ABSTRACT FROM AUTHOR]

In this study, we designed a 6T‐SRAM cell using 16‐nm CMOS process and analyzed the performance in terms of read‐speed latency. The temperature‐dependent Cu and multilayered graphene nanoribbon (MLGNR)‐based nano‐interconnect materials is used throughout the circuit (primarily bit/bit‐bars [red lines] and word lines [write lines]). Here, the read speed analysis is performed with four different chip operating temperatures (150K, 250K, 350K, and 450K) using both Cu and graphene nanoribbon (GNR) nano‐interconnects with different interconnect lengths (from 10 μm to 100 μm), for reading‐0 and reading‐1 operations. To execute the reading operation, the CMOS technology, that is, the16‐nm PTM‐HPC model, and the16‐nm interconnect technology, that is, ITRS‐13, are used in this application. The complete design is simulated using TSPICE simulation tools (by Mentor Graphics). The read speed latency increases rapidly as interconnect length increases for both Cu and GNR interconnects. However, the Cu interconnect has three to six times more latency than the GNR. In addition, we observe that the reading speed latency for the GNR interconnect is ~10.29 ns for wide temperature variations (150K to 450K), whereas the reading speed latency for the Cu interconnect varies between ~32 ns and 65 ns for the same temperature ranges. The above analysis is useful for the design of next generation, high‐speed memories using different nano‐interconnect materials. [ABSTRACT FROM AUTHOR]

The voyage of semiconductor industry to decrease the size of transistors to achieve superior device performance seems to near its physical dimensional limitations. The quest is on to explore emerging material systems that offer dimensional scaling to match the silicon- based technologies. The discovery of atomic flat two-dimensional materials has opened up a completely new avenue to fabricate transistors at sub-10 nanometer level which has the potential to compete with modern silicon-based semiconductor devices. Molybdenum disulfide (MoS2) is a two-dimensional layered material with novel semiconducting properties at atomic level seems like a promising candidate that can possibly meet the expectation of Moore's law. This review discusses the various ' fabrication challenges ' in making MoS2 based electronic devices from start to finish. The review outlines the intricate challenges of substrate selection and various synthesis methods of mono layer and few-layer MoS2. The review focuses on the various techniques and methods to minimize interface defect density at substrate/MoS2 interface for optimum MoS2-based device performance. The tunable band-gap of MoS2 with varying thickness presents a unique opportunity for contact engineering to mitigate the contact resistance issue using different elemental metals. In this work, we present a comprehensive overview of different types of contact materials with myriad geometries that show a profound impact on device performance. The choice of different insulating/dielectric gate oxides on MoS2 in co-planar and vertical geometry is critically reviewed and the physical feasibility of the same is discussed. The experimental constraints of different encapsulation techniques on MoS2 and its effect on structural and electronic properties are extensively discussed. [ABSTRACT FROM AUTHOR]

The impact of mini-field plated tapered T-Gate and conventional gate on LG = 50 nm AlGaN/GaN on - Silicon High Electron Mobility Transistor (HEMT) is analyzed and its DC/RF performance is reported in this work. The AlGaN/GaN HEMT supported with mini-filed plated tapered T- gate structure provides a maximum drain current of 1.53 A/mm when compared to conventional gate structure HEMT which is 0.8 A/mm. This work also examines, a brief analysis of mini-filed plated tapered T-gate structured HEMT for different work functions and different temperatures. The novel mini-filed plated tapered T-Gate structured HEMT on Silicon offers a higher cutoff frequency fT of 264 GHz and maximum oscillation frequency fMAX of 312 GHz which provides a great potential for future beyond 5G (B5G) applications. [ABSTRACT FROM AUTHOR]

The RF/DC performances of LG = 19 nm heterogeneous integrated Ga0.15In0.85As/InAs/Ga0.15In0.85As composite channel based InP HEMT (high electron mobility transistor) on Si (Silicon) wafer was investigated by using Sentaurus-TCAD simulations. In this research work, we systematically studied the impact of fixed negative charges (QF) at InP/SiO2 interface on the heterogeneous integrated transistor characteristics. The proposed heterogeneous integrated transistor on Si-wafer exhibited a transconductance (gm), drain current (IDS), fmax (maximum frequency of oscillation) and fT (cut-off frequency) of 1956 mS/mm, 1160 mA/mm, 576 GHz and 1138 GHz respectively with a QF of -5 × 1010/cm2 at InP/SiO2 interface. When QF was increased to -1 × 1012/cm2, gm, IDS, fT and fmax were degraded by 12%, 15%, 23.5% and 29.2% respectively due to the upward bending of EC (conduction band) energy level. The heterogeneous integrated Ga0.15In0.85As/InAs/Ga0.15In0.85As composite channel based InP HEMT on Si-substrate is considered as one of the most attractive transistors for future beyond 5G and quantum computing applications. [ABSTRACT FROM AUTHOR]

In this article, the high-k gate dielectric effect on the operation of complementary metal oxide semiconductor (CMOS) inverter build using conventional (CL) double-gate (DG) metal oxide semiconductor field effect transistor (MOSFET) and junctionless (JL) double-gate (DG) MOSFET has been explored. It is found that the improvement in inverter performance is more pronounced in CL-DG-MOSFET based CMOS inverter in comparison to JL-DG-MOSFET based CMOS inverter when SiO2 is replaced by the high-k dielectric at gate oxide. The improvement in low noise margin (ΔNML), high noise margin (ΔNMH), gain (ΔA) & propagation delay (ΔPd ) is 3.19%, 1.64%, 5.2% & 0.9% respectively when SiO2 is replaced by TiO2 at gate oxide in case of CL-DG-MOSFET based CMOS inverter whereas it is 1.96%, 1.24%, 3.4% & 1.71% respectively in case of JLDG-MOSFET based CMOS inverter. Consequently, the utilization of high-k dielectric as gate oxide is more advantageous in CL-DG-MOSFET devices for improved stability and gain of CMOS inverter. [ABSTRACT FROM AUTHOR]

This work investigates the channel thickness dependency of high-k gate dielectric-based complementary metal-oxide-semiconductor (CMOS) inverter circuit built using a conventional double-gate metal gate oxide semiconductor field-effect transistor (DG-MOSFET). It is espied that the use of high-k dielectric as a gate oxide in n/p DG-MOSFET based CMOS inverter results in a high noise margin as well as gain. It is also found that delay performance of the inverter circuit also gets upgraded slightly by using high-k gate dielectric materials. Further, it is observed that the scaling down of channel thickness (TSi) improves the noise margin (NM), and gain (A) at the cost of propagation delay (Pd ). Moreover, it is also observed that the changes in noise margin (ΔNM = NM(K=40) – NM(K=3.9)), propagation delay (ΔPd = Pd (K=40) – Pd (K=3.9)), and gain (ΔA = A(K=40) – A(K=3.9)) gets hinder at lower TSi. Therefore, it is apposite to look at lower channel thickness (~6 nm) while designing high-k gate dielectric-based DG-MOSFET for CMOS inverter cell. [ABSTRACT FROM AUTHOR]

This work investigates the delay performance of junctionless silicon nanotube (JLSiNT) field-effect transistor (FET) based 6T SRAM cell. The study demonstrates that the delay performance of symmetric drain/source DS-JLSiNT FET (inner gate covers drain, channel, and source regions) based 6T SRAM gets improved when the inner gate of nanotube covers only either drain and channel regions (D-JLSiNT FET) or source and channel regions (S-JLSiNT FET) because of improved Ion/Cgg. The improvement in read (write) access time is ~22% (17%) and ~9% (20%) when DS-JLSiNT FET is replaced by D-JLSiNT FET and S-JLSiNT FET, respectively, in DS-JLSiNT FET based 6T SRAM. Furthermore, due to partial covering of inner gate, the gate electrostatic integrity is reduced which decreases the ratio of on-current to off-current (Ion/Ioff) resulting in degraded static noise margin (SNM). However, the deterioration in write SNM, hold SNM, and read SNM are almost minimal (~0.3, 0.9, and 2%, respectively) for S-JLSiNT FET based SRAM as compared to DS-JLSiNT FET based SRAM. However, the deterioration in SNMs is aggravated for D-JLSiNT FET based SRAM as compared to DS-JLSiNT FET based SRAM. Thus, S-JLSiNT FET is the best configuration for designing of JLSiNT FET based 6T SRAM cell. [ABSTRACT FROM AUTHOR]

In this work, the investigation of high-K gate-stack-based junctionless (JL) double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) is carried out to study the high-K gate dielectric effect on six-transistor (6T)-static random-access memory (SRAM) built with JLDG-MOSFET. It is observed that the utilisation of the high-K gate dielectric in JLDG-MOSFETs improves the static noise margin (SNM) that is the stability of the cell as well as access time (AT) which reflects the delay performance of the SRAM cell. Furthermore, scaling down of Lg degrades the stability. Moreover, it is also described that the enhancement in hold SNM (ΔHSNM= HSNM(K=40)-HSNM(K=3.9)), read SNM (ΔRSNM=RSNM(K=40)-RSNM(K=3.9)), and write SNM (ΔWSNM=WSNM(K=40)-WSNM(K=3.9)) is restricted at lower Lg without much enhancement in the improvement of read AT and write AT. Therefore, it is appropriate to consider higher channel length (~30 nm) while designing high-K gate-stacked-based JLDG-MOSFETs for the 6T-SRAM cell. [ABSTRACT FROM AUTHOR]

This article is an editorial published in Frontiers in Manufacturing Technology, discussing the topic of life cycle engineering in the era of Industry 4.0. The editorial highlights the need for industries to modernize their life cycle engineering strategies in order to achieve sustainability and a competitive edge. It emphasizes the importance of integrating machine learning, modern computing technologies, and information management to optimize the product life cycle. The editorial also mentions several research articles that have been published on this topic, including studies on preventive maintenance, semantic interoperability, nested lifecycles, and energy consumption prediction models. The article concludes by stating that the field of digital transformation in the engineering life cycle is constantly growing, and more intriguing outcomes are expected in the future. [Extracted from the article]

The design of a high-performance Dielectrically Modulated Field Effect Transistor (DMFET) with smaller device dimension (channel length ≤ 100nm) has recently drawn significant research attention for point-of-care (POC) diagenesis applications. Driven by this paradigm, a Hetero-Gate Metal Dielectrically Modulated Junction-Less Nanotube Field Effect Transistor (DM-JLNFET) architecture is introduced and systematically investigated for label-free electrochemical biosensing application with the help of extensive numerical device simulations. The DM-JLNFET is carefully designed to exploit the advantages of superior gate control over channel electrostatics and electron injection component as well as strong immunity towards the short channel effects that lead to a notably high sensing performance compared to its conventional counterparts. In this context, the underlying physics of the transduction mechanism is analyzed in detail based on the device electrostatics and the carrier transport mechanism. The sensing performance of the proposed biosensor is quantified in terms of the drain current and threshold voltage sensitivities, which represents the relative modulations in these parameters with biomolecule conjugation. Typically, the DM-JLNFET exhibits a drain current and threshold voltage sensitivities as high as 1×10 12 and 0.70, respectively, for biomolecule dielectric constant above 2. Furthermore, the sensing performance demonstrates strong immunities towards non-uniform cavity occupancy. Finally, extensive comparative performance analysis with Dielectrically Modulated Nanowire Field Effect Transistor (DM-NWFET) is performed. The results exhibit that the proposed DM-JLNFET can offer more than 100% and eight orders of magnitude improvements in the threshold voltage and drain current sensitivities, respectively, for a range of small biomolecule dielectric constants.