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Abstract: The Quality of Service Network on Chip (QNoC) is the most perferment solution that provides low latency transfers and power efficient System on Chip (SoC) interconnect. This study presents [...]

Emerging nonvolatile memories (NVM) based on resistive switching mechanism such as RRAM are under intense R&D investigation by both academics and industries. They provide high write/read speed, low power, and good endurance (e.g., >1012) beyond mainstream NVMs, enabling them to be a good candidate for Flash replacement in microcontroller unit. This replacement could significantly decrease the power consumption and the integration cost on advanced CMOS nodes. This paper presents first the HfO2-based RRAM technology and the associated compact model, which includes related physics and model card fitting experimental electrical characterizations. The 128 kb memory architecture based on RRAM technology and 28 nm fully depleted silicon on insulator (FDSOI) CMOS core process is presented with a bottom-up approach, starting from the bit-cell definition up to the complete memory architecture implementation. The key points of the architecture are the use of standard logic MOS exclusively, avoiding any high voltage MOS usage, program/verify procedure to mitigate cycle to cycle variability issue and direct bit-cell read access for characterization purpose. The proposed architecture is validated using postlayout simulations on MOS and RRAM corner cases. [ABSTRACT FROM PUBLISHER]

Embedded processor is often expected to achieve a higher security with good performance and economical use of resource. However, the choice regarding the best solution for how cryptographic algorithms are incorporated in processor core is one of the most challenging assignments a designer has to face. This paper presents an inexpensive instruction set extensions (ISE) of efficient cryptographic algorithms on 32-bit processors assuring various types of instruction (public/private key cryptography, random number generator (RNG) and secure hash function (SHF)). These extensions provide hardware instructions that implement a full algorithm in a single instruction. Our enhanced LEON2 SPARC V8 core with cryptographic ISE is implemented using Xilinx XC5VFX70t FPGA device and an ASIC CMOS 40-nm technology. The total area of the resulting chip is about 1.93 mm2 and the estimated power consumption of the chip is 16.3 mW at 10 MHz. Hardware cost and power consumption evaluation are provided for different clock frequencies and the achieved results show that our circuit is able to be arranged in many security constrained devices. [ABSTRACT FROM AUTHOR]

We present a study of the effects of active queue management (AQM) on the average queue size in routers. In this work, three prominent AQM schemes are considered: packet classification, checking service level agreements (SLA) and queue scheduling. This paper presents several adaptive resource sharing models that use a revenue criterion to allocate bandwidth in an optimal way. The models ensure QoS requirements of data flows and, at the same time, maximize the total revenue by adjusting parameters of the underlying schedulers. Deficit round robin (DRR) and deficit weighted round robin (DWRR) scheduling techniques have shown their ability in providing fair and weighted sharing of network resources for network devices. However, they are unable to use the total allocated network bandwidth even in burst traffic. In this paper, we propose a negative-deficit weighted round robin (N-DWRR) technique as a new packet scheduling discipline to improve the bandwidth utilization rate without increasing the total latency. A fully hardware packet scheduler has been implemented and verified as part of an intellectual property core. This is motivated by the fact that the design and analysis of hardware/software architectures for such techniques requires new models and methods, which do not fall under the domain of traditional embedded-systems design. [ABSTRACT FROM AUTHOR]

An evident trend in modern world is the digital convergence in the current electronic consumer products which have various functions like Video on Demand (VOD), Digital Multimedia Broadcasting (DMB), Global Positioning System (GPS), Portable Multimedia Player (PMP) and so on. Due to such demand, it is necessary to support the widely used video compression standards in a single system-on-chip (SoC) platform. In this paper, we present a costsharing and adaptive GFS (Gradient-Four Search) architecture that integrates the gradient and the four step search algorithms to support the slow and rapid H264AVC video sequences. The proposed architecture can be configured dynamically by the appropriate algorithm depending on the video nature (slow or rapid). It uses only one data path to reduce the hardware cost significantly and it is based on stoppable clock technique to reduce dissipated power. The shared architecture is synthesized in CMOS 0.35 nm technology. The results show that the proposed design satisfies the requirement of the two types of video sequences with a maximum PSNR video quality. The scheme is also suitable for low-cost implementation in modern multi-codec systems. [ABSTRACT FROM AUTHOR]

This paper presents an interactive communication synthesis approach for multiprocessor systems. The aim of the approach consists in mapping a high level specification into a modular and flexible target architecture. The input specification is composed of a set of finite state machines that communicate via a procedural call mechanism. If we assume that the communication critical part is done through a shared memory, this approach allows us to refine the communication structures (interfaces, controllers) in order to reach an operational model easily mappable onto the target architecture. While the choice of communication protocols influences what the best partition is, the target architecture is extendible in order to minimize the communication cost that can be added by the partitioning. The proposed approach is validated through the design of a communication controller. [ABSTRACT FROM AUTHOR]