46 results on '"Sunil P. Khatri"'
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2. An ASIC Accelerator for QNN With Variable Precision and Tunable Energy Efficiency.
3. A Mixed-Signal Quantized Neural Network Accelerator Using Flash Transistors.
4. A Digital Low Dropout (LDO) Voltage Regulator Using Pseudoflash Transistors.
5. A Novel ASIC Design Flow Using Weight-Tunable Binary Neurons as Standard Cells.
6. Hardware Acceleration of Hash Operations in Modern Microprocessors.
7. A Novel ASIC Design Flow using Weight-Tunable Binary Neurons as Standard Cells.
8. CIDAN: Computing in DRAM with Artificial Neurons.
9. A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells.
10. Fast, Ring-Based Design of 3-D Stacked DRAM.
11. A GPU-CPU heterogeneous algorithm for NGS read alignment.
12. Comparing Leakage Reduction Techniques for an Asynchronous Network-on-Chip Router.
13. A Survey of Software and Hardware Approaches to Performing Read Alignment in Next Generation Sequencing.
14. Threshold Logic in a Flash.
15. FTCAM: An Area-Efficient Flash-Based Ternary CAM Design.
16. Using GPUs to Accelerate CAD Algorithms.
17. On Optimal and Achievable Fix-Free Codes.
18. A DCVSL Delay Cell for Fast Low Power Frequency Synthesis Applications.
19. Noise-based Deterministic Logic and Computing: a Brief Survey.
20. A Simultaneous Input Vector Control and Circuit Modification Technique to Reduce Leakage with Zero Delay Penalty.
21. Fault Table Computation on GPUs.
22. FPGA-based hardware acceleration for Boolean satisfiability.
23. Circuit-Level Design Approaches for Radiation-Hard Digital Electronics.
24. Efficient On-Chip Crosstalk Avoidance CODEC Design.
25. A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations.
26. Selective Forward Body Bias for High Speed and Low Power SRAMs.
27. Encoding Serial Graphical Data for Energy-Delay Product/Energy Minimization.
28. A Timing-Driven Approach to Synthesize Fast Barrel Shifters.
29. SAT-based ATPG using multilevel compatible don't-cares.
30. Resource sharing among mutually exclusive sum-of-product blocks for area reduction.
31. A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic.
32. Dynamically De-Skewable Clock Distribution Methodology.
33. A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations.
34. Efficient, scalable hardware engine for Boolean satisfiability and unsatisfiable core extraction.
35. Response to 'Comment on 'Zero and negative energy dissipation at information-theoretic erasure''.
36. A Predictably Low-Leakage ASIC Design Style.
37. High-throughput VLSI Implementations of Iterative Decoders and Related Code Construction Problems.
38. SPFD-based wire removal in standard-cell and network-of-PLA circuits.
39. Zero and negative energy dissipation at information-theoretic erasure.
40. An efficient and regular routing methodology for datapath designsusing net regularity extraction.
41. Noise-based information processing: Noise-based logic and computing: what do we have so far?
42. Boolean Satisfiability using Noise Based Logic
43. Towards brain-inspired computing
44. Computation using Noise-based Logic: Efficient String Verification over a Slow Communication Channel
45. Instantaneous noise-based logic
46. Noise-based deterministic logic and computing: a brief survey
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