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Fully integrated SONOS memory cell arrays with BT (body tied)-FinFET structure have been fabricated successfully by using manufacturable NOR flash technology. The uniformity of threshold voltage (Vth) distribution of the fabricated FinFET SONOS cells is fairly better than that of conventional flash cells thanks to both the widening effective channel width of FinFET structure and negligible coupling interference of SONOS device. New two-step channel implantation process has been introduced for the compensation for the boron out-diffusion of a three-dimensional silicon fin structure. The measured FinFET SONOS cells with a two-step channel doping profile show the improved program and erase characteristics. For the improvement of program/erase and retention characteristics all together, we have investigated the modulation of erase bias condition with respect to back tunneling effect. [ABSTRACT FROM PUBLISHER]

In this paper, we have fabricated nanoscale silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory devices by means of the sidewall patterning technique. The fabricated SONOS devices have a 30-nm-long and 30-nm-wide channel with 2.3/12/4.5-nm-thick oxide/nitride/oxide film on fully depleted-silicon-on-insulator (FD-SOI) substrate. The short channel effect is well suppressed though devices have very short channel length and width. Also, the fabricated SONOS devices guarantee good retention and endurance characteristics. In 30-nm SONOS devices, channel hot electron injection program mechanism is inefficient and 2-b operation based on localized carrier trapping in the nitride film is difficult. The erase speed is improved by means of band-to-band (BTB) assisted hole injection mechanism. In 30-nm SONOS devices, program and erase operation can be performed efficiently with improved erase speed by combination of Fowler-Nordheim (F-N) tunneling program and BTB assisted hole injection erase mechanism because the entire channel region programmed by F-N tunneling can be covered by two-sided hole injection from source and drain. [ABSTRACT FROM PUBLISHER]

The island size dependence of the capacitance components of single-electron transistors (SETs) based on gate-induced Si islands was extracted from the electrical characteristics. In the fabricated SETs, the sidewall gate tunes the electrically induced tunnel junctions, and controls the phase of the Coulomb oscillation. The capacitance between the sidewall gate and the Si island extracted from the Coulomb oscillation phase shift of the SETs with sidewall depletion gates on a silicon-on-insulator nanowire was independent of the Si island size, which is consistent with the device structure. The Coulomb oscillation phase shift of the fabricated SETs has the potential for a complementary operation. As a possible application to single-electron logic, the complementary single-electron inverter and binary decision diagram operation on the basis of the Coulomb oscillation phase shift and the tunable tunnel junctions were demonstrated. [ABSTRACT FROM PUBLISHER]

Studies silicon single-electron transistors (SET) with sidewall depletion gates and their application to dynamic single-electron transistor logic. Device characteristics immune to the gate bias condition; Significance of SET; Feasibility of the dynamic four-input multifunctional SET logic circuit.

We investigate the retention reliability of a 51-nm-node 16-GB NAND Flash cell transistor comprising SiO2/AlxOy/SiO2 inter-poly dielectric (OAO IPD). Despite the fact that OAO IPD retains low trapping rate being beneficial to retention reliability, the trap sites are located on shallow energy level, yielding a large amount of trap-assisted tunneling current at high temperature. Therefore, experimental results show two incompatible data retention characteristics of OAO IPD, namely, 33% worse VTH shift at 200 °C 2-h bake and 53% improved VTH shift after week at 25 °C, when compared to the case of ONO IPD. [ABSTRACT FROM AUTHOR]

Proposes a multilevel vertical-channel silicon-oxide-nitride-oxide-silicon (MLVC-SONOS) memory cell fabricated using 0.12-micrometer silicon-on-insulator standard logic process for Flash memory cell with ultrahigh density. Key process flow and TEM images on MLVC-SONOS; Reduction of cell size; Endurance measurement method for multilevels.

Fundic gland polyps (FGPs) are currently the most common type of gastric polyps and are usually benign. However, although rare, gastric adenocarcinoma of FGP has been recently proposed as a new variant of gastric adenocarcinoma. Here we report the first case of a 49-year-old woman with focal signet ring cell carcinoma that arose from an FGP of the stomach. The tumor was completely excised by endoscopic snare polypectomy. FGPs should therefore be evaluated for malignant changes although they occur rarely, if the FGP has an erosive or irregular surface.