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This work studies differential pair circuits designed with Line tunnel field effect transistors (TFETs), comparing their suitability with conventional Point TFETs. Differential voltage gain (Ad), compliance voltage and sensitivity to channel length mismatch are analyzed experimentally for different temperatures. The first part highlights individual characteristics of Line TFETs, focusing on behaviors that affect analog circuits. In comparison to Point TFETs, Line TFETs present higher drive current, better transconductance and worse output conductance. In the second part, differential pairs are studied at room temperature for different dimensions and bias conditions. Line TFETs present the highest Ad, while Point TFET decrease the susceptibility to channel length mismatch. In the last part, the temperature impact is investigated. Based on the activation energy, the impact of band-to-band tunneling and trap-assisted tunneling is discussed for different bias conditions. A general equation is proposed, including the technology and the susceptibility to temperature and dimensions. It was observed that Line TFETs are a good option to design differential pairs with higher Ad and ON-state current than Point TFETs. [ABSTRACT FROM AUTHOR]

In this letter, we show that conventional III–V MOSFETs with moderate/high In content channels (In0.53Ga0.47As or In0.70Ga0.30As) at scaled nodes are incompatible with mobile SoC designs, which often operate at intermediate/high V{\mathrm {dd}} (0.7 V to $\geq 1$ V) to achieve high frequency including during burst-mode. The incompatibility is due to conventional III–V FETs having too small bandgap, and thus too high leakage when operated at the increased voltages. We show that FETs with a more optimal lower In content, In0.35Ga0.65As, have the necessary combination of larger bandgap (~Si) and sufficiently high injection velocity (~2.5 times Si) to enable both low leakage and high performance (versus Si), across the entire V{\mathrm {dd}} range of mobile SoC operation. We report for the first time the growth and characterization of ultra-thin In0.35Ga0.65As FETs with a standard 1nm EOT gate dielectric. Calibrated models show that In0.35Ga0.65As enables the highest performance at very low leakages at intermediate/high V{\mathrm {dd}} in short channel FETs. [ABSTRACT FROM PUBLISHER]

InGaAs homojunction Tunnel FET devices are demonstrated with sub-60 mV/dec Sub-threshold Swing (SS) measured in DC. A 54mV/dec SS is achieved at 100 pA/μm over a drain voltage range of 0.2-0.5 V. The SS remains sub-60 mV/dec over 1.5 orders of magnitude of current at room temperature. Trap-Assisted Tunneling (TAT) is found to be negligible in the device evidenced by low temperature dependence of the transfer characteristics. Equivalent Oxide Thickness (EOT) is found to play the major role in achieving sub-60 mV/dec performance. The EOT of the demonstrated devices is 0.8 nm. [ABSTRACT FROM AUTHOR]

When processing Si nanowire based Tunnel Field Effect Transistors (TFETS's), a significant reduction of B diffusion with decreasing nanowire diameter is observed and attributed to reduced transient enhanced diffusion close to the nanowire surface caused by the recombination and out-diffusion of excess self-interstitials. In this study, Ultra High Voltage Electron Microscopy (UHVEM) is used to study in situ the formation of self-interstitial clusters in nanowire based TFET containing samples prepared by Focused Ion Beam (FIB) thinning. Si nanowires with diameters ranging from 40 to 500 nm are irradiated in an UHVEM using different fluxes of 2 MeV electrons at temperatures between room temperature and 375 °C. A strong dependence of defect formation on nanowire radius and on dopant concentration and type is observed. The UHVEM observations are compared with simulations based on quasi-chemical reaction rate theory and with two dimensional dopant concentration distributions determined with high-vacuum Scanning Spreading Resistance Microscopy (SSRM). (© 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

Si nanowire-based Tunnel-Field Effect Transistor (TFET) characteristics are intensively studied as function of nanowire diameter and doping. A significant reduction of B diffusion with decreasing nanowire diameter is e.g. observed and attributed to reduced transient enhanced diffusion close to the nanowire surface caused by the recombination and out-diffusion of excess self-interstitials. In an Ultra High Voltage Electron Microscope (UHVEM), the formation of self-interstitial clusters can be studied in situ while varying e-beam flux, irradiation temperature, impurity concentration and capping layers surrounding the nanowires. Results are presented on {113}-defect formation in Si nanowires with diameters between 40 and 500 nm. The Si nanowires are embedded in SiO2 and are etched into an epitaxial Si stack on a heavily As doped Si substrate. The top layer of the epitaxial stack is in situ B doped or B implanted. In situ UHVEM studies are performed on focused ion beam prepared cross-section samples, irradiating with different fluxes of 2 MeV electrons between room temperature and 375 °C. A strong dependence of {113}-defect formation on nanowire radius and doping is observed. The observations are compared with simulations based on quasi-chemical reaction rate theory. (© 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

Typical contacts to n-Ge result in high specific contact resistivity (ρC) or rectifying behaviour due to Fermi level pinning (resulting in high barrier heights) and low dopant activation generally observed for n-Ge. In this work, we fabricated and studied ohmic contacts to n-type Ge prepared by Ni germanidation of samples with As ion implantation for two different approaches: (1) dopant activation by sub-melt laser anneal (LA) prior to germanidation and (2) Snowplow, i.e., dopant segregation during Ni germanidation without previous thermal activation. Low resistivity ohmic contacts of 8 × 10-7 Ω cm2 for LA and 2 × 10-5 Ω cm2 for Snowplow were obtained using circular transfer length method to determine ρC. We show contacts to be thermally stable to 350 °C. Furthermore, by studying the temperature dependence of ρC, we clarify that the underlying cause of the low contact resistivity for both approaches is the high active dopant concentration obtained. We find the results in both cases to be consistent with the thermionic field-emission mechanism for a barrier height of 0.75 eV and with active dopant concentrations of 3 × 1019 cm-3 for LA and 1.5 × 1019 cm-3 for Snowplow samples. [ABSTRACT FROM AUTHOR]

We report on the study of the electrical and material properties of n-Ge contacts with a thin Si-passivation layer. n-Ge contacts typically show Fermi-level pinning and low dopant activation which results in too large specific contact resistivities of >10-4 Ω cm2 and which impedes applications such as high performance Ge complementary metal-oxide semiconductor technology. In this work a thin in situ doped (1×1020 cm-3 of phosphorus) epitaxial Si-passivation layer is grown selectively on n-Ge, followed by a Ti/TiN stack deposition. The insertion of this thin Si-passivation layer reduces the pinning and activation limitation, achieving specific contact resistivity values of ∼1×10-6 Ω cm2. Physical modeling of the specific contact resistivities was performed, providing the insight validating the underlying explanation of the improvement. Key factors for the contact resistivity lowering are the good alignment of the Si and Ge conduction bands and the higher doping concentration achieved in Si. [ABSTRACT FROM AUTHOR]

In this letter, we investigate the impact of a hybridized strain technology on the performance of FinFET-based multigate field-effect transistors (MUGFETs). The technology combines the use of supercritical strained-silicon-on-insulator (SC-SSOI) and strained contact etch stop layers (CESLs). We will show that SC-SSOI (top plane orientation (100)/(110)) with tensile CESL (tCESL), when used for MUGFET, leads to higher improvement in electron mobility as compared to standard SOI with tCESL. Therefore, the combination of both mobility boosters is very beneficial for n-channel MOS MUGFET. However, the impact of compressive CESL on p-channel MOS (pMOS) performance is strongly reduced and becomes even negative when used on an SC-SSOI substrate. Local strain relief of the SC-SSOI substrate is mandatory in order to achieve good pMOS device performance. [ABSTRACT FROM AUTHOR]

In this letter, we investigate the influence of tensile and compressive SiN layers on the device performance of triple-gate devices with 60-nm fin height and fin widths down to 35 nm. It will be shown that even for narrow fin devices, the nMOS performance improvement can be as high as 20% with tensile strained layers. The improvement seen for pMOS is lower, about 10%. Next to that both compressive as well as tensile SiN layers can increase the pMOS on-state current. [ABSTRACT FROM AUTHOR]

In this letter, we have fabricated a functional FinFET ring oscillator with a physical gate length of 25 nm and a fin width of 10 nm, the smallest ever reported. We demonstrate that these narrow (Wfin = 10 nm) and tall (Hfin = 60-80 nm) fins can be reliably etched with controlled profiles and that they are required to keep the short-channel effects under control, resulting in drain. induced barrier leakage characteristics of 45 mV/V at Vdd = 1 V and Lg = 25 nm for the nFET. For these ultrathin (10 nm) fins, we have succeeded in properly setting the VT at 0.2 V without the use of metal gates. In addition to ring oscillators, we also have obtained excellent pFET FinFET devices at wider fin widths (Wfln = 65 nm) with Idsat = 380 µA/µm at Ioff = 60 nA/µm and Vdd = -1.2V. [ABSTRACT FROM AUTHOR]

We study in this paper the epitaxial growth and electrical characterization of an n+In 0.5 Ga 0.5 As/p+GaAs 0.5 Sb 0.5 Esaki diode lattice matched to (001)-oriented InP substrate. First, the effects of molecular beam epitaxy growth temperature and group-V growth rates on the GaAs x Sb 1− x composition are characterized by means of X-ray diffraction (XRD). It is found that GaAs x Sb 1− x lattice constant is mainly determined by the Sb 4 incorporation rather than the As 4 one. After optimization, high quality In 0.54 Ga 0.46 As(Si)/GaAs 0.52 Sb 0.48 (Be) heterostructure is confirmed by XRD, Transmission electron microscope (TEM) and Secondary Ion Mass Spectroscopy (SIMS) profiles meeting requirements for sub-60 mV/dec operating devices. Esaki tunnel diodes are then fabricated to be used as a prediction of Band-To-Band Tunneling (BTBT) for Tunnel Field-Effect transistors (TFETs). The results are compared to previously reported n+/p+In 0.5 Ga 0.5 As homojunction diodes, showing a ×60 factor improvement of BTBT current density for the same electric field with an excellent average Peak-to-Valley Current Ratio (PVCR) of 14. [ABSTRACT FROM AUTHOR]

Abstract: The performance of nanoelectronic devices critically depends on the distribution of charge carriers inside such structures. High-vacuum scanning spreading resistance microscopy (HV-SSRM) has established as the method of choice for quantitative 2D-carrier mapping in nanoscale devices during the last decade. However, due to the 3D-nature of these nanoscale device architectures, dopant incorporation and dopant diffusion mechanisms can vary for any of the three dimensions, depending on the particular processes used. Therefore, mapping of carriers in three dimensions with high spatial resolution is inevitable to study and understand the distribution of active dopants in confined 3D-volumes and ultimately to support the process development of next generation devices. In this work, we present for the first time an approach to extend the capabilities of SSRM from an inherent 2D-carrier profiling technique towards a quantitative 3D-characterization technique based on the example of a nanowire (NW)-based heterojunction (SiGe–Si) tunneling transistor. In order to implement a 3D-methodology with a 2D-imaging technique, we acquired 2D-carrier concentration maps on successive cross-section planes through the device of interest. This was facilitated by arranging several devices in a staggered array, allowing to produce a series of cross-sections with incremental offset by a single cleave. A dedicated interpolation algorithm especially suited for structures with rotational symmetry like NWs was developed in order to reconstruct a 3D-carrier distribution map. The validity of the method was assessed by proving the absence of variations in carrier distribution in the third dimension, as expected for NWs etched into a blanket stack. [Copyright &y& Elsevier]

Abstract: This work presents the analog performance of nMOS triple-gate FinFETs with high-κ dielectrics, TiN gate material and undoped body from DC measurements. Different fin widths and devices with and without halo implantation are explored. No halo FinFETs can achieve extremely large gain and improved unity gain frequency at similar channel length than halo counterparts. The FinFETs with 110nm long channel achieve an intrinsic gain of 25dB. Extremely large Early voltages have been measured on long channel nMOS with no halo and relatively wide fins compared to the results usually reported in the literature. The large Early voltage obtained suggests that the devices operate in the onset of volume inversion due to the low doping level of the device body. [Copyright &y& Elsevier]

The successful implementation of nanowire (NW) based field-effect transistors (FET) critically depends on quantitative information about the carrier distribution inside such devices. Therefore, we have developed a method based on high-vacuum scanning spreading resistance microscopy (HV-SSRM) which allows two-dimensional (2D) quantitative carrier profiling of fully integrated silicon NW-based tunnel-FETs (TFETs) with 2 nm spatial resolution. The key elements of our characterization procedure are optimized NW cleaving and polishing steps, the use of in-house fabricated ultra-sharp diamond tips, measurements in high vacuum and a dedicated quantification procedure accounting for the Schottky-like tip-sample contact affected by surface states. In the case of the implanted TFET source regions we find a strong NW diameter dependence of conformality, junction abruptness and gate overlap, quantitatively in agreement with process simulations. In contrast, the arsenic doped drain regions reveal an unexpected NW diameter dependent dopant deactivation. The observed lower drain doping for smaller diameters is reflected in the device characteristics by lower TFET off-currents, as measured experimentally and confirmed by device simulations.