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High-Performance Computing (HPC) systems are designed for large-scale processing and complex dataset analysis leveraging scalability, efficiency, and parallelism, often integrating specialized hardware structures such as Vector Processing Units (VPUs). As these systems have grown in complexity and scale, their vulnerability to errors and failures has become an important and complex issue in the HPC world. Our research addresses this challenge by exploring and implementing advanced fault tolerance techniques inside the Vitruvius+ architecture, a partial out-of-order Vector Processing Unit. To the best of our knowledge, this is the first full RTL-level implementation of instruction replication in an HPC-class vector processor for reliability. Specifically, we investigate the integration and interaction of redundancy mechanisms inside the most sensitive architectural units, obtaining a reduction of 75% in non-silent faults causing system failure, proven by an extensive fault injection simulation campaign, with a hardware overhead of only 7.5% and a negligible variation in clock frequency.

Increase in traffic volume causes current roads to become insufficient, reduces the comfort and safety and hence causes physiological and economic damage. For the solution to such traffic problems, the junctions that form corridors should be designed in concert with each other. The parameters such as delay and travel time can be used as the evaluation criteria of new solutions. This paper presented an Analytic Hierarchy Process (AHP) based decision for a corridor with four junctions in terms of travel time, average delay, queue length, CO emission, fuel consumption and traffic safety. Three alternative scenarios were taken into consideration for improving the performance of the corridor. The VISSIM simulations were conducted for three scenarios. The first alternative of "all junctions are roundabout" received the highest priority value and was the first choice between other alternatives according to AHP. [ABSTRACT FROM AUTHOR]

By the World Health Organization, traffic accidents in 2013 have been identified as "human-caused natural disaster". Since the parameters which cause traffic accidents are numerous, they have a complex structure and they have continuously been a source of interest for analysis by researchers. In this study, D100 (E80) State highway section (422 km) between Erzincan-Agri (Gürbulak) cities in Turkey was investigated by examining the statistical data obtained from Turkish Statistical Institute and Republic of Turkey General Directorate of Highways 12th Regional Directory. For each kilometer lane, widths, Annual Average Daily Traffic (AADT), the number of accident, injury and death, average velocity, distance (km), the number of links and junctions were determined. The methods of ANN (Artificial Neural Network), Poisson regression and multivariate regression were used to analyze above parameters. The methods used have been evaluated as per R2, MSE, AIC criteria. It has been found for the ANN method that R2 (0.93), MSE (0.004), in Poisson regression method R2 (0.57), MSE (0.33), and in the multivariable regression method R2 (0.61), MSE (0.26). The results showed that ANN models perform better than the multivariate regression in terms of traffic accidents. [ABSTRACT FROM AUTHOR]

Soft errors are an important challenge in contemporary microprocessors. Particle hits on the components of a processor are expected to create an increasing number of transient errors with each new microprocessor generation. In this paper we propose simple mechanisms that effectively reduce the vulnerability to soft errors In a processor. Our designs are generally motivated by the fact that many of the produced and consumed values in the processors are narrow and their upper order bits are meaningless. Soft errors canted by any particle strike to these higher order bits can be avoided by simply identifying these narrow values. Alternatively soft errors can be detected or corrected on the narrow values by replicating the vulnerable portion of the value inside the storage space provided for the upper order bits of these operands. We offer a variety of schemes that make use of narrow values and analyze their efficiency in reducing soft error vulnerability of level-1 data cache of the processor [ABSTRACT FROM PUBLISHER]