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Implantable cell replacement therapies promise to completely restore the function of neural structures, possibly changing how we currently perceive the onset of neurodegenerative diseases. One of the major clinical hurdles for the routine implementation of stem cell therapies is poor cell retention and survival, demanding the need to better understand these mechanisms while providing precise and scalable approaches to monitor these cell-based therapies in both pre-clinical and clinical scenarios. This poses significant multidisciplinary challenges regarding planning, defining the methodology and requirements, prototyping and different stages of testing. Aiming toward an optogenetic neural stem cell implant controlled by a smart wireless electronic frontend, we show how an iterative development methodology coupled with a modular design philosophy can mitigate some of these challenges. In this study, we present a miniaturized, wireless-controlled, modular multisensor platform with fully interfaced electronics featuring three different modules: an impedance analyzer, a potentiostat and an optical stimulator. We show the application of the platform for electrical impedance spectroscopy-based cell monitoring, optical stimulation to induce dopamine release from optogenetically modified neurons and a potentiostat for cyclic voltammetry and amperometric detection of dopamine release. The multisensor platform is designed to be used as an opto-electric headstage for future in vivo animal experiments. [ABSTRACT FROM AUTHOR]

Pseudo-resistor circuits are used to mimic large value resistors and base their success on the reduction of occupied areas with respect to physical devices of equal value. This article presents an optimized architecture of pseudo-resistor, made in standard CMOS 0.35 $\mu \text{m}$ technology to bias a low-noise transimpedance amplifier for high-sensitivity applications in the frequency range 100 kHz–10 MHz. The architecture was selected after a critical review of the different topologies to implement high-value resistances with MOSFET transistors, considering their performance in terms of linearity of response, symmetric dynamic range, frequency behavior, and simplicity of realization. The resulting circuit consumes an area of 0.017 mm2 and features a tunable resistance from ${20\quad \text {M} \Omega }$ to ${20\quad \text {G} \Omega }$ , dynamic offset reduction due to a more than linear $I$ – $V$ curve, and a high-frequency noise well below the one of a physical resistor of equal value. This latter aspect highlights the larger perspective of pseudo-resistors as building blocks in very low-noise applications in addition to the advantage in occupied areas they provide. [ABSTRACT FROM AUTHOR]

The architecture of a low‐leakage switch in complementary metal‐oxide‐semiconductor (CMOS) technology developed to implement long‐term analogue memories for low‐power applications is presented. The switch reduces the leakage current using a cascade of modified pass‐transistors without active circuits, thus producing a negligible power consumption. The technique is simple, modular, robust, and reduces the leakage current down to tens of aA at room temperature using a TSMC 0.18 µm technology. [ABSTRACT FROM AUTHOR]

In this article, a new current-mode, accurate, and fully programmable Interval Type-2 (IT2) membership function generator (MFG) in 0.18 m CMOS technology is presented. This IT2 fuzzifier is based on a Type-1(T1) fuzzifier that uses a new method for slope tuning. The proposed slope tuning method, leads to smaller active area and also significantly smaller total die area by reducing the number of required pins in comparison with previous methods. Small area, low power consumption, and especially suitable programming method, makes the proposed IT2 MFG suitable for fuzzifier block of general-purpose Fuzzy Logic Controllers (FLCs). The proposed IT2 MFG has an average power consumption of 570Wand has an area of 0.0183mm2. Simulation results using HSPICE in a typical 0.18 m CMOS technology are presented to analyze the behavior of designed circuits. [ABSTRACT FROM AUTHOR]

Analog implementation of fuzzy logic controllers (FLCs) is the most efficient method when speed, power, and area are critical. Inference engine (IE) usually takes a large part of total die area when the FLC has a large number of rules. In this paper, a method is proposed to reduce size of the IE in analog implementations of FLCs. Since only a small number of rules may be fired simultaneously, thus a few inference blocks (IBs) may work at the same time in an IE. In the proposed method, reduction in size of the IE is achieved by sharing a few IBs between a large number of rules. To test the proposed method, a standard FLC is designed using both the regular method and the proposed method. By using the proposed method, total power consumption and active area are reduced by factors of 2.31 and 2.15, respectively. Moreover, inference speed is improved by a factor of 3.8 and output error is reduced by a factor of 2.5. All simulations have been performed in HSPICE using level 49 models for 0.35 um CMOS process with a 3.3V power supply. [ABSTRACT FROM AUTHOR]

A novel topology for a high gain two‐stage amplifier is proposed. The proposed circuit is designed in a way that the non‐dominant pole is at output of the first stage. A positive capacitive feedback around the second stage introduces a left half‐plane zero, which cancels the phase shift introduced by the non‐dominant pole, considerably. The dominant pole is at the output node, which means that increasing the load capacitance has minimal effect on stability. Moreover, a simple and effective method is proposed to enhance slew rate. Simulation shows that slew rate is improved by a factor of 2.44 using the proposed method. The proposed amplifier is designed in a 0.18 µm complementary metal‐oxide‐semiconductor process. It consumes 0.86 mW power from a 1.8 V power supply and occupies 3038.5 µm2 of chip area. The DC gain is 82.7 dB and gain bandwidth (GBW) is 88.9 MHz when driving a 5 pF capacitive load. Also low frequency common‐mode rejection ratio and positive power supply rejection ratio are 127 and 83.2 dB, respectively. They are 24.8 and 24.2 dB at GBW frequency, which are relatively high and are other important properties of the proposed amplifier. Moreover, simulations show convenient performance of the circuit in process corners and also the presence of a mismatch. [ABSTRACT FROM AUTHOR]